EM78P258N
8-Bit Microprocessor with OTP ROM
ꢀ The IOCC0 register bits are set to all "1"
ꢀ The IOCD0 register bits are set to all "1"
ꢀ Bits 7, 5, and 4 of IOCE0 register is cleared
ꢀ Bit 5 and 4 of RC register is cleared
ꢀ RF and IOCF0 registers are cleared
Executing the “SLEP” instruction will assert the sleep (power down) mode. While
entering into sleep mode, the Oscillator, TCC, TCCA, TCCB, and TCCC are stopped.
The WDT (if enabled) is cleared but keeps on running.
During AD conversion, when “SLEP” instruction I set; the Oscillator, TCC, TCCA,
TCCB, and TCCC keep on running. The WDT (if enabled) is cleared but keeps on
running.
The controller can be awakened by-
Case 1 External reset input on /RESET pin
Case 2 WDT time-out (if enabled)
Case 3 Port 5 input status changes (if ICWE is enabled)
Case 4 AD conversion completed (if ADWE enable).
The first two cases (1 & 2) will cause the EM78P258N to reset. The T and P flags of R3
can be used to determine the source of the reset (wake-up). Cases 3, &4 are
considered the continuation of program execution and the global interrupt ("ENI" or
"DISI" being executed) decides whether or not the controller branches to the interrupt
vector following wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from address 0x06 (Case 3), and 0x0C (Case 4) after wake-up. If DISI is
executed before SLEP, the execution will restart from the instruction next to SLEP after
wake-up.
Only one of Cases 1 to 4 can be enabled before entering into sleep mode. That is:
Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the
EM78P258N can be awaken only with Case 1 or Case 2. Refer to the
section on Interrupt (Section 6.6 below) for further details.
Case [b] If Port 5 Input Status Change is used to wake-up EM78P258N and the ICWE
bit of RE register is enabled before SLEP. At the same time, the WDT must
be disabled. Hence, the EM78P258N can be awaken only with Case 3.
Wake-up time is dependent on oscillator mode. Under RC mode the reset
time is 32 clocks. In High XTAL mode, reset time is 2ms and 32clocks; and
in low XTAL mode, the reset time is 500ms.
30 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
