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EM78M612BCM 参数 Datasheet PDF下载

EM78M612BCM图片预览
型号: EM78M612BCM
PDF下载: 下载PDF文件 查看货源
内容描述: 通用串行总线微控制器系列 [Universal Serial Bus Microcontroller Series]
分类和应用: 微控制器光电二极管局域网可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 38 页 / 1272 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78M612  
Universal Serial Bus Microcontroller Series  
Detecting block will start to sample the P60 input signal and measure the high pulse or low  
pulse width. After detecting the transition of this signal and debouncing, the value of the  
counter will be loaded into the RA (if the signal is transiting from high to low) or RB (if the  
signal is transiting from low to high), and the counter is cleared to start counting from zero.  
Two interrupts are supported individually by RA and RB. After the PDA function is enabled  
(by setting IOCE[2] to 1), a default value is written to the High Pattern counter register and  
Low Pattern counter register. Then define the corresponding interrupt enable bits (IOCF[6]  
and IOCF[7]). When the counter value of one “H” pattern is bigger than the RA default value,  
then the High Pattern Detecting interrupt will be generated. Similarly, if the counter value of  
one “L” pattern is bigger than the RB default value, the Low Pattern Detecting interrupt will  
occur. Then, the EM78M612 will be notified that one successful pattern is received from P60.  
If these two interrupts are not used, they can be masked. The new counter value of a pattern  
will still be loaded to the RA and RB. The firmware must be made to poll and determines any  
changes to the value of these two registers.  
The sample clock is programmable with 8 frequencies to choose from.  
8.9 Pulse Width Modulation (PWM)  
8.9.1 Function Description  
In PWM mode, both of PWM1 (P64) and PWM2 (P65) produce up to a 8-bit resolution PWM  
output. PWM output has a duty cycle and keeps the output high.  
The PWM Period is defined as 0xFF * Timer Counter Clock. The Timer Counter clock  
source is controlled by Control Register IOC8S. For example; if the Clock source is 1MHz,  
then the Period will be 255µ seconds.  
Period = 255 * (1/Timer Counter Clock)  
Period (0xFF * Clock)  
Duty Cycle  
Fig.8.9.2 The PWM Output Timing  
The PWM duty cycle is defined by writing to the R8S/R9S Register for PWM1/PWM2.  
Duty Cycle = R8S * (1/Timer Counter Clock) for PWM1  
R9S * (1/Timer Counter Clock) for PWM2  
This specification may change without further notice.  
2004/4/28 V1.1  
32  
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