EM78M612
Universal Serial Bus Microcontroller Series
RC [2]
RC [3]
RC [4]
Host Suspend flag. If this bit is equal to 1, it indicates that USB bus has no traffic
for the specified period of 3.0 ms. This bit will also be cleared automatically when
a bus activity takes place. This bit is only readable.
Device Resume flag. This bit is set by firmware to general a signal to wake-up the
USB host and is cleared as soon as the USB Suspend signal becomes low. This
bit can only be set by firmware and cleared by the hardware.
Undefined Register. The default value is 0.
RC [5,6] EP0_R / EP1_R flag. These two bits inform the UDC to read the data written by
firmware from the FIFO. Then the UDC sends the data to the host automatically.
After UDC finishes reading the data from the FIFO, this bit is cleared
automatically.
Therefore, before writing data into the FIFO, the firmware will first check this bit to
prevent overwriting the existing data. These two bits can only be set by the
firmware and cleared by the hardware.
RC [7]
EP0_W flag. After the UDC completes writing data to the FIFO, this bit will be set
automatically. The firmware will clear it as soon as it gets the data from EP0’s
FIFO. Only when this bit is cleared that the UDC will be able to write a new data
into the FIFO.
Therefore, before the firmware can write a data into the FIFO, this bit must first be
set by the firmware to prevent UDC from writing data at the same time. This bit is
both readable and writable.
This specification may change without further notice.
2004/4/28 V1.1
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ELAN [ ELAN MICROELECTRONICS CORP ]
