EM78860
8-BIT MICRO-CONTROLLER
FUNCTION DESCRIPTION
Operational Registers
R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using
R0 as register actually accesses data pointed by the RAM Select Register (R4).
R1 (TCC)
• Increased by an internal signal edge applied to TCC , or by the instruction cycle clock.
• Written and read by the program as any other register.
R2 (Program Counter)
• The structure is depicted in Fig. 4.
• Generates 16Kx13 on-chip ROM addresses to the relative programming instruction codes.
• ”JMP” instruction allows the direct loading of the low 10 program counter bits.
• “CALL” instruction loads the low 10 bits of the PC, PC+1, and then push into the stack..
• “RET’’ (“RETL k”, “RETI”) instruction loads the program counter with the contents at the top of stack.
• ”MOV R2,A” allows the loading of an address from the A register to the PC, and the ninth and tenth bits are
cleared to “0'’.
• “ADD R2,A” allows a relative address be added to the current PC, and contents of the ninth and tenth bits are
cleared to “0'’.
• “TBL” allows a relative address be added to the current PC, and contents of the ninth and tenth bits don’t
change.
• The most significant bit (A10~A13) will be loaded with the content ofbit PS0~PS3 in the status register (R5)
upon the execution of a “JMP’’, “CALL’’, “ADD R2,A’’, or “MOV R2,A’’ instruction.
CALL
PC
A13 A12 A11 A10
A9 A8
A7~A0
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
Stack 6
Stack 7
Stack 8
RET
RETTL
RETI
0000 PAGE0 0000~03FF
0000 PAGE1 0400~07FF
0000 PAGE3 0800~0BFF
1110 PAGE14 3800~3BFF
1111 PAGE15 3C00~3FFF
Fig.4 Program counter organization
* This specification are subject to be changed without notice.
4
6.24.1998
ELAN [ ELAN MICROELECTRONICS CORP ]
