Contents
7.2.19 RD Port D I/O Data, Data RAM address...........................................................42
7.2.19.1 Page 0 Port D I/O Data, Data RAM Address .....................................42
7.2.19.2 Page 1 Data RAM Address 1 (Low 8 Bits).........................................42
7.2.19.3 Page 2 Undefined Register................................................................42
7.2.19.4 Page 3 Undefined Register................................................................42
7.2.20 RE Interrupt Flag 1, Data RAM Address 1 (H) CAS, Key Scan ........................42
7.2.20.1 Page 0 Interrupt Flag 1 ......................................................................42
7.2.20.2 Page 1 Data RAM Address 1(H)........................................................43
7.2.20.3 Page 2 CAS Detected Flag, Keyscan................................................43
7.2.20.4 Page 3 UART Transmitter Data Buffer...............................................46
7.2.21 RF Interrupt flag ................................................................................................46
7.2.21.1 Page 1 External Data ROM ...............................................................47
7.2.21.2 Page 2 External Data ROM ...............................................................47
7.2.21.3 Page 3 Unused ..................................................................................47
7.2.22 R10~R3F (General Purpose Register)..............................................................47
7.3 Special Purpose Registers................................................................................47
7.3.1 A (Accumulator).................................................................................................47
7.3.2 CONT (Control Register)...................................................................................48
7.3.3 IOC5AddressAutomatic Increase/Decrease Control, Data RAM Data Buffer 2...........49
7.3.3.1 Page 0 Address Automatic Increase/Decrease Control Register ......49
7.3.3.2 Page 1 Data RAM Data Buffer 2........................................................50
7.3.4 IOC6 Port 6 I/O Control, Data RAM Address (L)...............................................51
7.3.4.1 Page 0 Port 6 I/O Control...................................................................51
7.3.4.2 Page 1 Data RAM Address 2 (L)........................................................51
7.3.5 IOC7 PORT 7 I/O Control, Data RAM Address 2 (H)........................................51
7.3.5.1 Page 0 Port 7 I/O Control...................................................................51
7.3.5.2 Page 1 Data RAM Address 2 (H).......................................................51
7.3.6 IOC8 Port 8 I/O Control.....................................................................................52
7.3.6.1 Page 0 Port 8 I/O Control...................................................................52
7.3.6.2 Page 1 Undefined Register................................................................52
7.3.7 IOC9 Port 9 I/O Control.....................................................................................52
7.3.7.1 Page 0 Port 9 I/O Control...................................................................52
7.3.7.2 Page 1 Undefined Register................................................................52
7.3.8 IOCA Undefined Register..................................................................................52
7.3.9 IOCB Port B I/O Control, External LCD Driver Interface (for EMC 65×132).....53
7.3.9.1 Page 0 Port B I/O Control ..................................................................53
7.3.9.2 Page 1 External LCD Driver Controller..............................................53
7.3.10 IOCC Port C I/O Control, Port 6 Pull-high Register ..........................................56
7.3.10.1 Page 0 Port C I/O Control..................................................................56
7.3.10.2 Page 1 Port 6 Pull-high Register .......................................................56
7.3.11 IOCD Port D I/O Control, Port 7 Pull-high Register ..........................................56
7.3.11.1 Page 0 Port D I/O Control..................................................................56
7.3.11.2 Page 1 Port 7 Pull-high Register .......................................................57
Product Specification (V2.4) 02.17.2006
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ELAN [ ELAN MICROELECTRONICS CORP ]
