EM78808
8-bit Micro-controller
EVENT
T
P
REMARK
WDT wake up from sleep mode
WDT time out (not sleep mode)
/RESET wake up from sleep
Power up
0
0
1
1
x
0
1
0
1
Low pulse on /RESET
X
x : don't care
Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page
Please refer to Fig.4 control register configuration for details.
0/1 ꢂpage0 / page1
Bit 6(IOCP1S) : change IOC PAGE1 and PAGE2 to another option register
Please refer to Fig.4 control register configuration for details.
0/1 ꢂpage1 /page2
Bit 6(IOCP1S)
Bit 5 (IOCPAGE)
PAGE SELECT
PAGE 0
X
0
1
0
1
1
PAGE 1
PAGE 2
Bit 7(PAGE) : change R4 ~ RE to another page
Please refer to Fig.4 control register configuration for details.
0/1 ꢂpage0 / page1
R4 (RAM selection for common registers R20 ~ R3F, SPI)
PAGE0 (RAM selection register)
7
6
5
4
3
2
1
0
RB1
RB0
RSR5
RSR4
RSR3
RSR2
RSR1
RSR0
Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F
RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode.
Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F
These selection bits are used to determine which bank is activated among the 4 banks for 32 register (R20 to
R3F)..
Please refer to Fig.4 control register configuration for details.
PAGE1 (SPI control register)
7
6
5
4
3
2
1
0
RBF
SPIE
SRO
SE
SCES
SBR2
SBR1
SBR0
Fig. 6 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it
sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI, however, is
defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted on a basis
of both the clock rate and the selected edge.
______________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
8/1/2004 (V3.1)
14
ELAN [ ELAN MICROELECTRONICS CORP ]
