EM78468
8-BIT Microcontroller
4.8 Interrupt
This LSI has eight interrupt sources as listed below:
TCC overflow interrupt.
External interrupt P5.4/INTO pin
External interrupt P5.5/INT1 pin
Counter 1 underflow interrupt
Counter 2 underflow interrupt
High-pulse width timer underflow interrupt
Low-pulse width timer underflow interrupt
Port 6, Port 8 input status change wake-up
This IC has internal interrupts which are falling edge triggered or as follows:
TCC timer overflow interrupt,
Four 8-bits down-count timer underflow interrupt
If these interrupt sources change signal from high to low, the RF register will generate “1”
flag to corresponding register if the IOCF0 register is enabled.
RF is the interrupt status register. It records the interrupt request in flag bit. IOCF0 is the
interrupt mask register. Global interrupt is enabled by ENI instruction and disabled by
DISI instruction. When one of the interrupts (when enabled) is generated, it will cause the
next instruction to be fetch from address 0003H~0018H according to interrupt source.
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Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
