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EM77950 参数 Datasheet PDF下载

EM77950图片预览
型号: EM77950
PDF下载: 下载PDF文件 查看货源
内容描述: BB控制器 [BB Controller]
分类和应用: 控制器
文件页数/大小: 102 页 / 928 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM77950  
BB Controller  
Bit 7: CS  
This flag enables/disables the CS interrupt.  
CS flag in SSR negative edge triggers CS interrupt.  
8.4.2 Interrupt Identification Register (IIR)  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
TX  
AE  
RX  
AF  
TX  
LOCK  
OUT  
LOCK  
IN  
LINK_  
DIS  
IIR  
CS  
RX_OF  
EMPTY  
This is a read only register.  
When the MCU accesses the IIR, all interrupts freeze. While the MCU access is  
occurring, the system records the changes in the interrupts but waits until the MCU  
access is complete before updating the register. A flag is active only when the  
matching interrupt enable bit is set, and does not depend on the IE bit value. The flags  
are set by H/W and cleared after the MCU reads the register.  
Bit 0: This bit reflects the LOCK IN flag interrupt when enabled by IER.  
This bit reflects the LOCK IN flag interrupt when enabled by IER.  
LOCK_IN interrupt is invoke whenever a PREAMBLE+NET_ID+NODE_ID  
where recognized.  
If NET_ID is disabled, then a received PREAMBLE+ NODE_ID invokes the  
interrupt.  
If NODE_ID is disabled, then a received PREAMBLE+ NET_ID invokes the  
interrupt.  
If NET_ID and NODE_ID are disabled, then a received PREAMBLE invokes  
the interrupt.  
Bit 1: This bit reflects the LOCK OUT flag interrupt when enabled by IER.  
This bit reflects the LOCK OUT flag interrupt when enabled by IER.  
LOCK_OUT interrupt is invoked whenever RFW-D100 has finished receiving a  
packet. The end of the packet is determined according to the packet size.  
Bit 2: This bit reflects the LINK_DIS flag interrupt when enabled by IER.  
This interrupt is invoked by the zero counter capacitor discharge mechanism.  
Bit 3: This bit reflects the RX_OF flag interrupt when enabled by IER.  
Bit 4: This bit reflects the TX EMPTY flag interrupt when enabled by IER.  
Bit 5: This bit reflects the RX FIFO AF flag interrupt when enabled by IER.  
Bit 6: This bit reflects the TX FIFO AE flag interrupt when enabled by IER.  
Bit 7: CS – when CS flag goes from “1” to “0”, an interrupt is invoked.  
64 •  
Product Specification (V1.0) 10.09.2007  
(This specification is subject to change without further notice)  
 
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