EM65571
130COM/128SEG 65K Color STN LCD Driver
After completion of an 8-bit data transfer, or when making no access, be sure to set
the serial clock input (SCL) to “L”. Care of the SDA and SCL signals against
external noise should be taken into consideration during board wiring. To prevent
transfer error due to external noise, release the chip select (CSB = “H”) after every
completion of an 8-bit data transfer.
CSB
RS
D7
D6
D5
D4
D3
D2
D1
D0
SDA
SCL
1
2
3
4
5
6
7
8
Figure 4. 4-wire Type Serial Interface
7.1.7 3-Wire Type Serial Interface
When chip select is active (CSB = “L”), 3-wire type serial interface can work
through the SDA and SCL input pins. When chip select is inactive (CSB = “H”), the
internal shift register and counter are reset to the initial condition. Serial data SDA
is input sequentially in the order from RS, D7 to D0 at the rising edge of the serial
clock (SCL) and is converted into 9-bit parallel data (by serial to parallel
conversion) at the rising edge of the 9th serial clock. The identification whether
serial data input (SDA), display data or control register data is determined by the
first serial input data (RS) and SPOL pin as follows.
SPOL = “0”
SPOL = “1”
RS
0
Display RAM/Register
Display RAM Data
Control Register Data
RS
0
Display RAM/Register
Control Register Data
Display RAM Data
1
1
After completion of a 9-bit data transfer, or when making no access, be sure to set
the serial clock input (SCL) to “L”. Care of the SDA and SCL signals against
external noise should be taken into consideration during board wiring. To prevent
transfer error due to external noise, release the chip select (CSB = “H”) after every
completion of 9-bit data transfer.
Product Specification (V1.0) 08.04.2005
• 19
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
