EM65570
68COM/ 98SEG 65K Color STN LCD Driver
7.11.1 Signal Generation to Display Line Counter and Data
Latching Circuit
Clocks to the line counter and display data latching circuit from the display clock
(internal LP) are generated. Synchronized with the display clock (internal LP), the line
addresses of Display RAM are generated and the 384-bit display data is latched to the
display data latching circuit to output to the LCD drive circuit (Segment outputs).
Read-out of the display data to the LCD drive circuit is completely independent of MPU.
Therefore, MPU has no relationship with the read-out operation that accesses the
display data.
7.11.2 Generation of the Alternated Signal (internal M) and the
Synchronous Signal (internal FLM)
LCD alternated signal (internal M) and synchronous signal (internal FLM) are
generated by the display clock (internal LP). The FLM generates alternated drive
waveform to the LCD drive circuit. Normally, the FLM generates alternated drive
waveform every frame (M-signal level is reversed every one frame). However, when
setting up data (n-1) in an n-line reverse register and n-line alternated control bit (NLIN)
at “1,” the n-line reverse waveform is generated.
7.11.3 Display Data Latching Circuit
Display data latching circuit temporally latches the display data that is output to the
LCD driver circuit from display RAM every one common period. Normal
display/reverse display, display ON/OFF, and display ALL-ON functions are operated
by controlling data in display data latch. Therefore, there is no change of data within
the display RAM.
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Product Specification (V1.0) 09.05.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
