EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Toggle Bit Timing Diagram
A18~A0
TCE
CE#
TOES
TOE
TOEH
OE#
WE#
DQ6
Two Read Cycles
With Same Outputs
Figure 5: Toggle Bit Timing Diagram
WE# Controlled Chip-Erase Timing Diagram
TSCE
Six-Byte Code For Chip-Erase
5555
2AAA
5555
5555
2AAA
5555
A18~A0
CE#
OE#
TWP
WE#
AA
SW0
55
SW1
80
SW2
AA
SW3
55
SW4
10
SW5
DQ7-0
Note: This device also supports CE# controlled Chip-Erase operation. The WE#and CE#
signals are interchageable as long as minimum timings are met. (See Table 10)
Figure 6: WE# Controlled Chip-Erase Timing Diagram
This specification is subject to change without further notice. (07.22.2004 V1.0)
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ELAN [ ELAN MICROELECTRONICS CORP ]
