欢迎访问ic37.com |
会员登录 免费注册
发布采购

EM19101 参数 Datasheet PDF下载

EM19101图片预览
型号: EM19101
PDF下载: 下载PDF文件 查看货源
内容描述: 8位5 MSPS A / D转换器( CMOS ) [8-BIT 5 MSPS A/D CONVERTER (CMOS)]
分类和应用: 转换器
文件页数/大小: 6 页 / 109 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
 浏览型号EM19101的Datasheet PDF文件第1页浏览型号EM19101的Datasheet PDF文件第2页浏览型号EM19101的Datasheet PDF文件第3页浏览型号EM19101的Datasheet PDF文件第5页浏览型号EM19101的Datasheet PDF文件第6页  
EM19101  
8-BIT 5 MSPS A/D CONVERTER (CMOS)  
Parameter  
Digital output current  
Sym.  
IOH  
IOL  
Conditions  
OE=VSS,  
VDD=min.  
OE=VDD,  
Min. Typ. Max. Unit  
VOH=VDD-0.5V  
VOL=0.4V  
VOH=VDD  
-1.1  
3.7  
mA  
uA  
ns  
Digital output current  
IOZH  
16  
16  
40  
VOL=0V  
Output data delay  
TDL  
EL  
ED  
DG  
25  
Integral nonlinearity  
Differential nonlinearity  
Differential gain error  
FC=5MSPS VIN=0.6V to 2.6V  
FC=5MSPS VIN=0.6V to 2.6V  
NTSC 40 IRE mod ramp,  
FC=14.3MSPS  
0.5 1.3 LSB  
±0.3 ±0.5 LSB  
1.0  
0.5  
30  
4
%
°C  
ps  
ns  
Differential phase error  
Aperture jitter  
Sampling delay  
DP  
tAJ  
tDS  
Application Note  
VDD,VSS  
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and  
analog VDD pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the  
respective GND’s.  
Analog input  
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However  
it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When  
driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by  
inserting a resistance of about 100in series between the amplifier output and A/D input.  
Clock input  
The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate  
it from other circuits  
Reference input  
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and  
V
RB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VRT  
and VRTS, VRB and VRBS, the self bias function that generates VRT=2.6V and VRB=0.6V, is activated.  
Timing  
Analog input is sampled with the falling edge of external clock and output as digital data with a delay of 2.5  
clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 25ns.  
OE pin  
By connecting OE to GND output mode is obtained. By connecting to VDD high impedance is obtained.  
* This specification are subject to be changed without notice.  
4
4.23.1997