EDS6416AHTA-TI
Self Refresh Cycle
CLK
CKE
/CS
lSREX
CKE Low
/RAS
/CAS
/WE
BS
Address
A10=1
UDQM
LDQM
DQ (input)
High-Z
DQ (output)
t
RC
t
t
RC
RP
Self refresh cycle
/RAS-/CAS delay = 3
CL = 3
Auto
refresh
Self refresh entry
command
Precharge command
If needed
Next
Self refresh exit
ignore command
or No operation
Next
clock
enable
Self refresh entry
command
clock
enable
BL = 4
=
VIH or VIL
Clock Suspend Mode
tSI
tSI
10 11 12 13 14 15 16 17 18 19 20
tHI
0
1
2
3
4
5
6
7
8
9
CLK
CKE
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
/CS
/RAS
/CAS
/WE
BS
Address
R:a
C:a
R:b
C:b
UDQM, LDQM
DQ (output)
DQ (input)
a
a+1 a+2
a+3
b
b+1 b+2 b+3
High-Z
Bank0 Active clock
Active suspend start
Active clock Bank0
suspend end Read
Bank3 Read suspend Read suspend
Bank0
Earliest Bank3
Precharge
Bank3
Active
start
end Read Precharge
CKE
Write cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
/CS
/RAS
/CAS
/WE
BS
R:b
a+1
Address
UDQM, LDQM
R:a
C:a
a
C:b
High-Z
DQ (output)
DQ (input)
a+2
a+3
b
b+1 b+2 b+3
Bank0
Active clock Bank0 Bank3 Write suspend Write suspend Bank3
Earliest Bank3
Precharge
Bank0 Active clock
Active suspend start
Precharge
end Write
supend end Write Active
start
Preliminary Data Sheet E0636E10 (Ver.1.0)
44
ELPIDA [ ELPIDA MEMORY ]
