EDJ1108BABG, EDJ1116BABG
Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V ± 0.075V)
Parameter
Input pin capacitance, CK and /CK
DDR3-1600, 1333
DDR3-1066, 800
Delta input pin capacitance, CK and /CK
DDR3-1600, 1333
DDR3-1066, 800
Input pin capacitance, control pins
DDR3-1600, 1333
Symbol
CCK
Pins
min.
0.8
0.8
0
max.
1.4
Unit
pF
pF
pF
pF
pF
pF
Notes
1, 3
1, 3
1, 2
1, 2
1
1.6
CK, /CK
0.15
0.15
1.3
CDCK
0
0.75
0.75
CIN_CTRL
/CS, CKE, ODT
DDR3-1066, 800
1.5
1
Input pin capacitance, address and
command pins
0.75
1.3
pF
1
CIN_ADD_CMD
CDIN_CTRL
/RAS, /CAS, /WE, Address
/CS, CKE, ODT
DDR3-1600, 1333
DDR3-1066, 800
Delta input pin capacitance, control pins
DDR3-1600, 1333
0.75
−0.4
−0.5
1.5
0.2
0.3
pF
pF
pF
1
1, 4
1, 4
DDR3-1066, 800
Delta input pin capacitance, address and
command pins
DDR3-1600, 1333
−0.4
0.4
pF
1, 5
CDIN_ADD_CMD /RAS, /CAS, /WE, Address
DDR3-1066, 800
Input/output pin capacitance
DDR3-1600
−0.5
0.5
2.3
pF
pF
1, 5
1, 6
1.5
CIO
DDR3-1333
1.5
1.5
2.5
3.0
pF
pF
1, 6
1, 6
DQ, DQS, /DQS,
TDQS, /TDQS
DM
DDR3-1066, 800
Delta input/output pin capacitance
DDR3-1600, 1333
DDR3-1066, 800
Delta input/output pin capacitance
DDR3-1600, 1333
−0.5
−0.5
0
0.3
pF
pF
pF
1, 7, 8
1, 7, 8
1, 10
CDIO
0.3
0.15
CDDQS
CZQ
DQS, /DQS
ZQ
DDR3-1066, 800
0
0.2
3
pF
pF
1, 10
1, 9
Input/output pin capacitance of ZQ
Notes: 1. VDD, VDDQ, VSS, VSSQ applied and all other pins (except the pin under test) floating.
VDD = VDDQ =1.5V, VBIAS=VDD/2
2. Absolute value of CCK(CK-pin) − CCK(/CK-pin)
3. CCK (min.) will be equal to CIN (min.)
4. CDIN_CTRL = CIN_CTRL − 0.5 × (CCK(CK-pin) + CCK(/CK-pin))
5. CDIN_ADD_CMD = CIN_ADD_CMD − 0.5 × (CCK(CK-pin) + CCK(/CK-pin))
6. Although the DM, TDQS and /TDQS pins have different functions, the loading matches DQ and DQS.
7. DQ should be in high impedance state.
8. CDIO = CIO (DQ, DM) −0.5 × (CIO(DQS-pin) + CIO(/DQS-pin)).
9. Maximum external load capacitance on ZQ pin: 5pF.
10 Absolute value of CIO(DQS) − CIO(/DQS)
Data Sheet E1248E40 (Ver. 4.0)
45
ELPIDA [ ELPIDA MEMORY ]
