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EDJ1108BABG-DG-E 参数 Datasheet PDF下载

EDJ1108BABG-DG-E图片预览
型号: EDJ1108BABG-DG-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 148 页 / 1878 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDJ1108BABG, EDJ1116BABG  
AC and DC Logic Input Levels for Differential Signals  
Differential signal definition  
Definition of Differential AC-swing and “time above AC-level” tDVAC  
[Differential AC and DC Input Levels]  
Parameter  
Symbol  
VIHdiff  
VILdiff  
min.  
typ.  
max.  
Unit  
V
Notes  
3
Differential input logic high  
Differential input logic low  
Differential input logic AC  
Differential input logic AC  
+0.200  
*
1
1
2
2
3
*
–0.200  
V
3
VIHdiff (AC) 2 × (VIH (AC) VREF)  
*
V
3
VILdiff (AC)  
*
2 × (VREF VIL(AC))  
V
Notes: 1 Used to define a differential signal slew-rate.  
2. For CK, /CK use VIH/VIL(AC) of address/command and VREFCA; for strobes (DQS, /DQS, DQSL,  
/DQSL, DQSU, /DQSU) use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is  
used for a signal group, then the reduced level applies also here.  
3
These values are not defined, however the single ended components of differential signal CK, /CK, DQS,  
/DQS, DQSL, /DQSL, DQSU, /DQSU need to be within the respective limits (VIH(DC) max, VIL(DC)min)  
for single-ended signals as well as the limitations for overshoot and undershoot. Refer to Overshoot and  
Undershoot specifications.  
Data Sheet E1248E40 (Ver. 4.0)  
16  
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