EDJ1108BABG, EDJ1116BABG
• CK, /CK crossing to DQS, /DQS crossing
• tDQSCK; rising edges only of CK and DQS
• tQSH; rising edges of DQS to falling edges of DQS
• tQSL; rising edges of / DQS to falling edges of /DQS
• tLZ (DQS), tHZ (DQS) for preamble/postamble (see tHZ (DQS), tLZ (DQS)
RL Measured to this point
CK
/CK
tDQSCK(min.)
tDQSCK(min.)
tDQSCK(min.)
tDQSCK(min.)
tLZ(DQS)(min.)
tQSL
tQSH
tRPRE
tRPST
DQS, /DQS
Early strobe
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
tDQSCK(max.)
tDQSCK(max.)
tQSL
tDQSCK(max.) tDQSCK(max.)
tLZ(DQS)(max.)
tHZ(DQS)(max.)
tQSH
tRPRE
tRPST
DQS, /DQS
Late strobe
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Notes: Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min.) or tDQSCK(max.).
Instead, rising strobe edge can vary between tDQSCK(min.) or tDQSCK(max.) within a burst.
Likewise tLZ(DQS)(min.) and tHZ(DQS)(min.) are not tied to tDQSCK(min.) (early strobe case) and
tLZ(DQS)(max.) and tHZ(DQS)(max.) are not tied to tDQSCK(max.) (late strobe case).
The minimum pulse width of read preamble is defined by tRPRE(min.).
The minimum pulse width of read preamble is defined by tRPST(min.).
DDR3 Clock to Data Strobe Relationship
Data Sheet E1248E40 (Ver. 4.0)
99
ELPIDA [ ELPIDA MEMORY ]
