EDJ1108BABG, EDJ1116BABG
Asynchronous to Synchronous ODT Mode during Short CKE high and Short CKE Low Periods
If the total time in precharge power-down state or idle state is very short, the transition periods for power-down entry
and power-down exit may overlap. In this case the response of the DDR3 SDRAM RTT to a change in ODT state at
the input may be synchronous OR asynchronous from the start of the power-down entry transition period to the end
of the PD exit transition period (even if the entry period ends later than the exit period).
If the total time in idle state is very short, the transition periods for power-down exit and power-down entry may
overlap. In this case the response of the DDR3 SDRAM RTT to a change in ODT state at the input may be
synchronous OR asynchronous from the start of the power-down exit transition period to the end of the power-down
entry transition period.
Note that in the bottom part of figure below it is assumed that there was no refresh command in progress when idle
state was entered.
CK
/CK
Command
REF
NOP NOP
NOP NOP
CKE
tANPD
tRFC
PD entry transition period
PD exit transition period
tXPDLL
tANPD
short CKE low transition period
CKE
tANPD
tXPDLL
tXPDLL
tANPD
short CKE high transition period
Transition Period for Short CKE Cycles with Entry and Exit Period Overlapping
(AL = 0, WL = 5, tANPD = WL − 1 = 4)
Data Sheet E1248E40 (Ver. 4.0)
141
ELPIDA [ ELPIDA MEMORY ]
