EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
DDR3 SDRAM Mode Register 2 [MR2]
The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and /CAS write
latency (CWL). The Mode Register 2 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA1 and low on
BA0, while con-trolling the states of address pins according to the table below.
Address field
BA2 BA1 BA0 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0*1
1
0
Mode register 2
0*1
Rtt_WR*2
0*1 SRT ASR
CWL
PASR* 2
A7
Self-refresh range
Normal self-refresh
Partial array self-refresh
A2 A1 A0
0
1
Refresh array
Extend temperature
self-refresh
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full
(BA [2:0]
(BA [2:0]
(BA [2:0]
(BA [2:0]
(BA [2:0]
(BA [2:0]
(BA [2:0]
=
=
=
=
=
=
=
000, 001, 010, 011)
000, 001)
Half
: Bank 0 to Bank 3
Quarter: Bank 0 and Bank 1
000)
1/8
3/4
Half
: Bank 0
A6 Auto self-refresh method
010, 011, 100, 101,110 ,111)
100, 101, 110, 111)
110, 111)
: Bank 2 to Bank 7
: Bank 4 to Bank 7
Manual SR reference
0
(SRT)
ASR enable
1
Quarter: Bank 6 and Bank 7
1/8 : Bank 7
(Optional)
111)
A5
0
A4
0
A3
0
CAS write Latency (CWL)
5 (tCK ≥ 2.5ns)
A10 A9
Rtt_WR
0
0
Dynamic ODT off (write does not
affect Rtt value)
0
0
1
6 (2.5ns > tCK≥ 1.875ns)
7 (1.875ns > tCK≥ 1.5ns)
8 (1.5ns > tCK≥ 1.25ns)
Reserved
0
1
0
0
1
1
1
0
1
RZQ/4
RZQ/2
0
1
1
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Notes: 1. BA2, A8, and A11 to A13 are RFU and must be programmed to 0 during MRS.
2. The Rtt_WR value can be applied during writes even when Rtt_Nom is desabled.
Dring write leveling, Dynamic ODT is not avaiable.
3. Optiona in DDR3 SDRAM: If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond
the specified address range will be lost if self-refresh is entered. Data integrity will be maintained if tREF conditions are
met and no self-refresh command is issued.
MR2 Programming
Data Sheet E1375E50 (Ver. 5.0)
80
ELPIDA [ ELPIDA MEMORY ]
