EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Pin Configurations (×4, ×8 configuration)
/xxx indicates active low signal.
78-ball FBGA (×4 configuration)
78-ball FBGA (×8 configuration)
1
2
3
7
8
9
1
2
3
7
8
9
A
B
A
B
VSS
VDD
NC
NC
VSS
VDD
VSS
VDD
NC
NU/(/TDQS) VSS
VDD
VSS VSSQ DQ0
DM VSSQ VDDQ
VSS VSSQ DQ0
VDDQ
DM/TDQS VSSQ VDDQ
C
D
C
D
VDDQ
VSSQ
DQ2 DQS
NC /DQS
DQ1
VDD
NC
DQ3 VSSQ
VSSQ
NC VDDQ
NC
VDD CKE
DQ2 DQS
DQ1
VDD
DQ7
DQ3 VSSQ
VSSQ
VSS
VSSQ DQ6 /DQS
VSS
DQ5
E
F
G
H
J
E
F
G
H
J
DQ4
VREFDQ VDDQ NC
NC VSS /RAS
ODT VDD /CAS
VREFDQ VDDQ
VDDQ
NC
CK
/CK
VSS
NC
VSS /RAS
CK
/CK
VSS
ODT VDD /CAS
VDD CKE
A10(AP)
A10(AP)
NC
/CS
/WE
ZQ
NC
NC
/CS
/WE
ZQ
NC
VSS
VDD
VSS
VDD
VSS
BA0
A3
BA2
A0
NC VREFCA VSS
VSS
VDD
VSS
VDD
VSS
BA0
A3
BA2
A0
NC VREFCA VSS
K
L
K
L
A12(/BC) BA1
VDD
VSS
VDD
VSS
A12(/BC) BA1
VDD
VSS
VDD
VSS
A5
A2
A1
A11
NC
A4
A6
A8
A5
A2
A1
A11
NC
A4
A6
A8
M
N
M
N
A7
A9
A7
A9
/RESET A13
/RESET A13
(Top view)
(Top view)
Pin name
Function
Pin name
/RESET*3
Function
Address inputs
A10 (AP): Auto precharge
A12(/BC): Burst chop
A0 to A13*3
Active low asynchronous reset
Supply voltage for internal
circuit
BA0 to BA2*3
Bank select
VDD
DQ0 to DQ7
DQS, /DQS
TDQS, /TDQS
/CS*3
Data input/output
Differential data strobe
Termination data strobe
Chip select
VSS
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
VDDQ
VSSQ
VREFDQ
VREFCA
Reference voltage for DQ
Reference voltage
/RAS, /CAS, /WE*3
Command input
Reference pin for ZQ
calibration
No connection
CKE*3
Clock enable
ZQ
CK, /CK
DM
ODT*3
Differential clock input
Write data mask
ODT control
NC*1
NU*2
Not usable
Notes: 1. Not internally connected with die.
2. Don’t connect. Internally connected.
3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1375E50 (Ver. 5.0)
3
ELPIDA [ ELPIDA MEMORY ]
