EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Timing Values tXXXPDEN Parameters
Status of DRAM
Idle or Active
Idle or Active
Active
Last Command before CKE_low
Parameter
tACTPDEN
tPRPDEN
tRDPDEN
Parameter Value
Unit
nCK
nCK
nCK
Activate
1
1
Precharge
READ/READA
RL + 4 + 1
WL + 4 + (tWR/tCK (avg))
Active
Active
WRIT for BL8MRS, BL8OTF, BC4OTF tWRPDEN
nCK
nCK
1
*
WL + 2 + (tWR/tCK
WRIT for BC4MRS
tWRPDEN
(avg))*1
Active
Active
Idle
WRITA for BL8MRS, BL8OTF, BC4OTF tWRAPDEN
WL + 4 + WR*2 + 1
nCK
nCK
nCK
WRITA for BC4MRS
Refresh
tWRAPDEN
tREFPDEN
tMRSPDEN
WL + 2 + WR*2 + 1
1
Idle
Mode Register Set
tMOD
Notes: 1. tWR is defined in ns, for calculation of tWRPDEN, it is necessary to round up tWR / tCK to next integer.
2. WR in clock cycles as programmed in mode register.
Power-Down Entry and Exit Clarification
Case 1:
When CKE registered low for power-down entry, tPD must be satisfied before CKE can be registered high for power-
down exit.
Case 1a:
After power-down exit, tCKE must be satisfied before CKE can be registered low again.
T0
T1
Tn
Tn+1
Tx
Ty
CK
/CK
tIH
tIH
CKE
tIS
tIS
tPD
tCPDED
NOP NOP NOP
tCKE
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
N
Command
Exit power-down
Enter power-down
Power-Down Entry/Exit Clarifications (1)
Data Sheet E1375E50 (Ver. 5.0)
130
ELPIDA [ ELPIDA MEMORY ]
