EDE5104AGSE, EDE5108AGSE
Asynchronous CKE Low Event
DRAM requires CKE to be maintained high for all valid operations as defined in this data sheet. If CKE
asynchronously drops low during any valid operation DRAM is not guaranteed to preserve the contents of array. If
this event occurs, memory controller must satisfy DRAM timing specification tDELAY before turning off the clocks.
Stable clocks must exist at the input of DRAM before CKE is raised high again. DRAM must be fully re-initialized
(steps 4 through 13) as described in initialization sequence. DRAM is ready for normal operation after the
initialization sequence. See AC Characteristics table for tDELAY specification
Stable clocks
tCK
/CK
CK
tDELAY
CKE
CKE asynchronously
drops low
Clocks can be
turned off after
this point
Preliminary Data Sheet E0715E20 (Ver. 2.0)
60
ELPIDA [ ELPIDA MEMORY ]
