EDE1104ACSE, EDE1108ACSE, EDE1116ACSE
Block Diagram
CK
/CK
CKE
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
A0 to A13,
BA0, BA1, BA2
Row
address
Memory cell array
Bank 0
buffer
and
refresh
counter
Mode
register
Sense amp.
Column decoder
Column
address
buffer
and
/CS
/RAS
/CAS
/WE
burst
counter
Data control circuit
Latch circuit
DQS, /DQS
RDQS, /RDQS
CK, /CK
DLL
Input & Output buffer
ODT
DM
DQ
Data Sheet E0975E50 (Ver.5.0)
29