EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
/CK
CK
VIH
CKE
/CS
/RAS
/CAS
/WE
BA
Address
DM
code
code
C: b
R: b
valid
High-Z
High-Z
DQS
b
DQ (output)
tMRD
tRP
Bank 3
Read
Bank 3
Precharge
Mode
register
set
Bank 3
Active
CL = 2
BL = 4
Precharge
If needed
= VIH or VIL
Read/Write Cycle
/CK
CK
VIH
CKE
/CS
/RAS
/CAS
/WE
BA
Address
R:a
C:b''
C:a R:b
C:b
DM
DQS
a
b’’
DQ (output)
DQ (input)
High-Z
b
tRWD
tWRD
Bank 0
Active
Bank 0 Bank 3
Read Active
Bank 3
Write
Bank 3
Read
Read cycle
CL = 2
BL = 4
=VIH or VIL
Preliminary Data Sheet E0501E10 (Ver. 1.0)
43