EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
CK
/CK
READ
NOP
Command
DQS
tRPRE
tRPST
VTT
CL = 2
tAC,tDQSCK
tRPRE
VTT
VTT
out0 out1 out2 out3
DQ
tRPST
DQS
CL = 2.5
tAC,tDQSCK
VTT
out0 out1 out2 out3
DQ
Read Operation (/CAS Latency)
Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by
the column address, the bank select address which are loaded via the A0 to A12, BA0 to BA1 pins in the cycle when
the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst
operation. tWPRE prior to the first rising edge of the DQS should be set to Low and tWPST after the last falling edge
of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low
period of DQS is referred as write postamble.
t0
t1
tn tn+0.5 tn+1
tn+2
tn+3
tn+4
tn+5
CK
/CK
tRCD
NOP
Command
Address
NOP
ACT
Row
WRITE
NOP
Column
tWPRE
tWPRES
in0 in1
BL = 2
tWPST
DQS
DQ
in0 in1 in2 in3
BL = 4
BL = 8
in0 in1 in2 in3 in4 in5 in6 in7
BL: Burst length
Write Operation
Preliminary Data Sheet E0501E10 (Ver. 1.0)
24
ELPIDA [ ELPIDA MEMORY ]
