欢迎访问ic37.com |
会员登录 免费注册
发布采购

EDD5108ADTA-6BL-E 参数 Datasheet PDF下载

EDD5108ADTA-6BL-E图片预览
型号: EDD5108ADTA-6BL-E
PDF下载: 下载PDF文件 查看货源
内容描述: 512M比特DDR SDRAM [512M bits DDR SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器双倍数据速率时钟
文件页数/大小: 49 页 / 549 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDD5108ADTA-6BL-E的Datasheet PDF文件第7页浏览型号EDD5108ADTA-6BL-E的Datasheet PDF文件第8页浏览型号EDD5108ADTA-6BL-E的Datasheet PDF文件第9页浏览型号EDD5108ADTA-6BL-E的Datasheet PDF文件第10页浏览型号EDD5108ADTA-6BL-E的Datasheet PDF文件第12页浏览型号EDD5108ADTA-6BL-E的Datasheet PDF文件第13页浏览型号EDD5108ADTA-6BL-E的Datasheet PDF文件第14页浏览型号EDD5108ADTA-6BL-E的Datasheet PDF文件第15页  
EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E  
Pin Function  
CK, /CK (input pins)  
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point  
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point  
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the  
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock  
input to this pin. The other input signals are referred at CK rising edge.  
/CS (input pin)  
When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal  
operations (bank active, burst operations, etc.) are held.  
/RAS, /CAS, and /WE (input pins)  
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.  
See "Command operation".  
A0 to A12 (input pins)  
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the  
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0  
to the A9, A11 and A12 at the cross point of the CK rising edge and the /CK falling edge in a read or a write  
command cycle. This column address becomes the starting address of a burst operation.  
[Address Pins Table]  
Address (A0 to A12)  
Part number  
EDD5104AD  
EDD5108AD  
EDD5116AD  
Row address  
AX0 to AX12  
AX0 to AX12  
AX0 to AX12  
Column address  
AY0 to AY9, AY11, AY12  
AY0 to AY9, AY11  
AY0 to AY9  
A10 (AP) (input pin)  
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If  
A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge  
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write  
command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled.  
BA0 and BA1 (input pins)  
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See  
Bank Select Signal Table)  
[Bank Select Signal Table]  
BA0  
L
BA1  
L
Bank 0  
Bank 1  
H
L
Bank 2  
L
H
Bank 3  
H
H
Remark: H: VIH. L: VIL  
Preliminary Data Sheet E0501E10 (Ver. 1.0)  
11