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EDD5104ABTA-7B 参数 Datasheet PDF下载

EDD5104ABTA-7B图片预览
型号: EDD5104ABTA-7B
PDF下载: 下载PDF文件 查看货源
内容描述: 512M比特DDR SDRAM [512M bits DDR SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器双倍数据速率时钟
文件页数/大小: 50 页 / 438 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDD5104ABTA, EDD5108ABTA  
Command Intervals  
A Read command to the consecutive Read command Interval  
Destination row of the  
consecutive read command  
Bank  
address  
Row address State  
Operation  
The consecutive read can be performed after an interval of no less than 1 cycle to  
interrupt the preceding read operation.  
Precharge the bank to interrupt the preceding read operation. tRP after the  
precharge command, issue the ACT command. tRCD after the ACT command, the  
consecutive read command can be issued. See ‘A read command to the  
consecutive precharge interval’ section.  
The consecutive read can be performed after an interval of no less than 1 cycle to  
interrupt the preceding read operation.  
Precharge the bank without interrupting the preceding read operation. tRP after  
the precharge command, issue the ACT command. tRCD after the ACT command,  
the consecutive read command can be issued.  
1. Same  
Same  
Different  
Any  
ACTIVE  
2. Same  
3. Different  
ACTIVE  
IDLE  
t0  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
CK  
/CK  
Command  
NOP  
ACT  
Row  
NOP  
READ  
READ  
Column A Column B  
Address  
BA  
out out out out out out  
A0 A1 B0 B1 B2 B3  
DQ  
Column = A Column = B  
Read  
Read  
Column = A  
Dout  
Column = B  
Dout  
DQS  
CL = 2  
BL = 4  
Bank0  
Bank0  
Active  
READ to READ Command Interval (same ROW address in the same bank)  
Preliminary Data Sheet E0237E30 (Ver. 3.0)  
28  
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