EDD2516AKTA-E
Operation of the DDR SDRAM
Power-up Sequence
(1)Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined).
Apply VDD before or at the same time as VDDQ.
Apply VDDQ before or at the same time as VTT and VREF.
(2) Start clock and maintain stable condition for a minimum of 200 µs.
(3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high.
(4) Issue precharge all command for the device.
(5) Issue EMRS to enable DLL.
(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of
clock input is required to lock the DLL after every DLL reset).
(7) Issue precharge all command for the device.
(8) Issue 2 or more auto-refresh commands.
(9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting
the DLL.
(4)
(5)
(6)
(7)
(8)
(9)
CK
/CK
Any
command
Command
PALL
EMRS
MRS
PALL
REF
REF
REF
MRS
t
t
t
RFC
2 cycles (min.) 2 cycles (min.) 2 cycles (min.)
DLL enable
DLL reset with A8 = High
2 cycles (min.)
RP
RFC
Disable DLL reset with A8 = Low
200 cycles (min)
Power-up Sequence after CKE Goes High
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating
mode. Parameters are set to both through the A0 to the A12 and BA0, BA1 pins by the mode register set command
[MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are
set by inputting signal via the A0 to the A12 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine
which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode
register must be set.
Remind that no other parameters are shown in the table bellow are allowed to input to the registers.
BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4
DR LMODE
A3
BT
A2 A1
BL
A0
0
0
0
0
0
0
0
MRS
A6 A5 A4 CAS Latency
A8 DLL Reset
A3 Burst Type
Burst Length
BT=0 BT=1
A2 A1 A0
2
0
1
1
1
0
0
0
1
No
0
1
Sequential
Interleave
2.5
2
4
8
2
4
8
0
0
0
0
1
1
1
0
1
Yes
Mode Register Set [MRS] (BA0 = 0, BA1 = 0)
Data Sheet E0502E30 (Ver. 3.0)
21
ELPIDA [ ELPIDA MEMORY ]
