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EDD1208ALTA-7A 参数 Datasheet PDF下载

EDD1208ALTA-7A图片预览
型号: EDD1208ALTA-7A
PDF下载: 下载PDF文件 查看货源
内容描述: 128 M位同步DRAM是双倍数据速率( 4 -银行, SSTL_2 ) [128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2)]
分类和应用: 存储内存集成电路光电二极管动态存储器双倍数据速率时钟
文件页数/大小: 78 页 / 1650 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDD1204ALTA, EDD1208ALTA, EDD1216ALTA  
16. Revision History  
Version /  
Page  
Description  
Location  
Date  
This edition Previous  
edition  
Type of  
revision  
Ver. 1.0 /  
April. 2001  
Ver. 2.0 /  
May. 2001  
27  
29  
36  
41  
42  
46  
55  
56  
60  
65  
66  
69  
70  
38  
39  
27  
29  
36  
41  
42  
46  
55  
56  
60  
65  
66  
69  
70  
38  
39  
Modification  
Modification  
Modification  
Modification  
Modification  
Modification  
Modification  
Modification  
Modification  
Modification  
Modification  
Modification  
Modification  
Addition  
Figure of Write to Precharge Command Interval  
Figure of Write with Auto precharge  
Figure of Precharge Termination in Write Cycle  
tCK (CL = 2.5) (MIN.) : 8 ns to 10 ns  
tWR (MIN.) : 15/15/15 ns to 2/2/2 CLK  
AC Parameters for Write Timing  
Random Column Write (1/2)  
Random Column Write (2/2)  
Random Row Write (2/2)  
Interleaved Column Write Cycle (1/2)  
Interleaved Column Write Cycle (2/2)  
Auto Precharge after Write Burst (1/2)  
Auto Precharge after Write Burst (2/2)  
DC Characteristics specification  
Ver. 3.0  
October 2001  
Modification  
VIH (ac) (MIN.): VREF + 0.35 to VREF + 0.31  
VIL (ac) (MAX.): VREF + 0.35 to VREF - 0.31  
tHP (MIN.): tCH, tCL to MIN. (tCH, tCL)  
41  
42  
42  
45  
41  
42  
42  
45  
Modification  
Modification  
Modification  
Modification  
tWPRE (MIN.) (tCK = 7.5ns): 0.25 ns to 1.88 ns  
tDAL (MIN.): TBD to 35 ns  
[tDAL]: to 5/5/5/4/4/4  
76  
Preliminary Data Sheet E0136E30  
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