EBJ21RE8BAFA
Block Diagram
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
VTT
VDDSPD
VREFCA
VREFDQ
VDD
SPD
SDRAMs (D0 to D17)
SDRAMs (D0 to D17)
SDRAMs (D0 to D17)
VSS
SDRAMs (D0 to D17), SPD
CK1
Teminated at near
card edge
/CK1
Note :
R
S2
1. DQ wiring may be changed within a byte.
/CS0*2
/CS1*2
BA
/RCS0_A -> /CS: SDRAMs D0 to D3, D8
/RCS0_B -> /CS: SDRAMs D4 to D7
R
S2
* D0 to D17: 1G bits DDR3 SDRAM
Address, BA: A0 to A15, BA0 to BA2
Command: /RAS, /CAS, /WE
U1: 256 bytes EEPROM
Rs1: 15
Rs2: 22
Rs3: 39
Rs4: 120
Rs5: 240
Serial PD
SCL
SDA
/RCS1_A -> /CS: SDRAMs D9 to D12, D17
/RCS1_B -> /CS: SDRAMs D13 to D16
SCL
SA0
SDA
R
S2
R
S2
R
S2
R
S2
R
S2
RBA_A -> BA0 to BA2: SDRAMs D0 to D3, D8 to D12, D17
RBA_B -> BA0 to BA2: D4 to D7, D13 to D16
A0
U1
A1
A2
SA1
SA2
Address
Command
CKE0
RAddress_A -> A0 to A13: SDRAMs D0 to D3, D8 to D12, D17
RAddress_B -> A0 to A13: SDRAMs D4 to D7, D13 to D16
/EVENT
/EVENT
RCommand_A -> /RAS, /CAS, /WE: SDRAMs D0 to D3, D8 to D12, D17
RCommand_B -> /RAS, /CAS, /WE: SDRAMs D4 to D7, D13 to D16
Register: SSTE32882
RCKE0_A -> CKE: SDRAMs D0 to D3, D8
RCKE0_B -> CKE: SDRAMs D4 to D7
R
E
G
I
CKE1
RCKE1_A -> CKE: SDRAMs D9 to D12, D17
RCKE1_B -> CKE: SDRAMs D13 to D16
S
T
E
R
R
S2
R
S2
ODT0
RODT0_A -> ODT: SDRAMs D0 to D3, D8
RODT0_B -> ODT: SDRAMs D4 to D7
D9
D10 D11 D12 D17
D13 D14 D15 D16
ODT1
RODT1_A -> ODT: SDRAMs D9 to D12, D17
RODT1_B -> ODT: SDRAMs D13 to D16
/
P
L
L
PCK0_A -> CK: SDRAMs D0 to D3, D8
PCK0_B -> CK: SDRAMs D4 to D7
PCK1_A -> CK: SDRAMs D9 to D12, D17
PCK1_B -> CK: SDRAMs D13 to D16
CK0
Register
D0
D1
D2
D3
D8
D4
D5
D6
D7
/PCK0_A -> /CK: SDRAMs D0 to D3, D8
/CK0
/PCK0_B -> /CK: SDRAMs D4 to D7
/PCK1_A -> /CK: SDRAMs D9 to D12, D17
/PCK1_B -> /CK: SDRAMs D13 to D16
/Err_Out
R
S2
Address, command and control line
Par_In
/RESET
/RESET
/RESET: SDRAMs D0 to D17
Data Sheet E1251E40 (Ver. 4.0)
10
ELPIDA [ ELPIDA MEMORY ]
