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EBJ21UE8BDS1-AE-F 参数 Datasheet PDF下载

EBJ21UE8BDS1-AE-F图片预览
型号: EBJ21UE8BDS1-AE-F
PDF下载: 下载PDF文件 查看货源
内容描述: 2GB DDR3 SDRAM SO- DIMM [2GB DDR3 SDRAM SO-DIMM]
分类和应用: 内存集成电路光电二极管动态存储器双倍数据速率时钟
文件页数/大小: 18 页 / 196 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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DATA SHEET  
2GB DDR3 SDRAM SO-DIMM  
EBJ21UE8BDS1 (256M words × 64 bits, 2 Ranks)  
Specifications  
Features  
Density: 2GB  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 8 bits  
prefetch pipelined architecture  
256M words × 64 bits, 2 ranks  
Mounting 16 pieces of 1G bits DDR3 SDRAM sealed  
in FBGA  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
Package: 204-pin socket type small outline dual in  
line memory module (SO-DIMM)  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
PCB height: 30.0mm  
Lead pitch: 0.6mm  
Differential clock inputs (CK and /CK)  
Lead-free (RoHS compliant) and Halogen-free  
Power supply: VDD = 1.5V ± 0.075V  
Data rate: 1333Mbps/1066Mbps (max.)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Eight internal banks for concurrent operation  
(components)  
Data mask (DM) for write data  
Interface: SSTL_15  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
Burst lengths (BL): 8 and 4 with Burst Chop (BC)  
/CAS Latency (CL): 5, 6, 7, 8, 9  
/CAS write latency (CWL): 5, 6, 7  
On-Die-Termination (ODT) for better signal quality  
Synchronous ODT  
Dynamic ODT  
Precharge: auto precharge option for each burst  
access  
Asynchronous ODT  
Refresh: auto-refresh, self-refresh  
Refresh cycles  
Multi Purpose Register (MPR) for temperature read  
out  
ZQ calibration for DQ drive and ODT  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Programmable Partial Array Self-Refresh (PASR)  
/RESET pin for Power-up sequence and reset  
Operating case temperature range  
TC = 0°C to +95°C  
function  
SRT range:  
Normal/extended  
Programmable Output driver impedance control  
Document No. E1623E20 (Ver. 2.0)  
Date Published April 2010 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2010