EBJ20UF8BDU0
Serial PD Matrix
-DJ
-GN
Byte
No.
Function described
Hex Comments
Hex Comments
Number of serial PD bytes written/SPD device
size/CRC coverage
0
92h 176/256/0-116
92h 176/256/0-116
1
SPD revision
10h Rev.1.0
10h Rev.1.0
2
Key byte/DRAM device type
Key byte/module type
0Bh DDR3 SDRAM
03h SO-DIMM
03h 2G bits, 8 banks
19h 15 rows, 10 columns
00h 1.5V
0Bh DDR3 SDRAM
03h SO-DIMM
03h 2G bits, 8 banks
19h 15 rows, 10 columns
00h 1.5V
3
4
SDRAM density and banks
SDRAM addressing
5
6
Module nominal voltage, VDD
Module organization
7
01h 1 rank/×8 bits
03h 64 bits/non-ECC
52h 5/2
01h 1 rank/×8 bits
03h 64 bits/non-ECC
52h 5/2
8
Module memory bus width
9
Fine timebase (FTB) dividend/divisor
Medium timebase (MTB) dividend
Medium timebase (MTB) divisor
SDRAM minimum cycle time (tCK (min.))
Reserved
10
11
12
13
14
15
16
17
01h 1
01h 1
08h 8
08h 8
0Ch1.5ns
0Ah 1.25ns
00h —
00h —
SDRAM CAS latencies supported, LSB
SDRAM CAS latencies supported, MSB
SDRAM minimum CAS latencies time (tAA (min.))
7Eh 5, 6, 7, 8, 9, 10
00h —
FEh5, 6, 7, 8, 9, 10, 11
00h —
69h 13.125ns
69h 13.125ns
78h 15ns
SDRAM minimum write recovery time (tWR (min.)) 78h 15ns
SDRAM minimum /RAS to /CAS delay
18
19
69h 13.125ns
69h 13.125ns
30h 6ns
(tRCD (min.))
SDRAM minimum row active to row active delay
(tRRD (min.))
30h 6ns
20
21
SDRAM minimum row precharge time (tRP (min.))
SDRAM upper nibbles for tRAS and tRC
69h 13.125ns
11h —
69h 13.125ns
11h —
SDRAM minimum active to precharge time
(tRAS (min.)), LSB
22
23
24
25
26
20h 36ns
18h 35ns
SDRAM minimum active to active /auto-refresh time
(tRC (min.)), LSB
89h 49.125ns
00h 160ns
05h 160ns
3Ch7.5ns
81h 48.125ns
00h 160ns
05h 160ns
3Ch7.5ns
SDRAM minimum refresh recovery time delay
(tRFC (min.)), LSB
SDRAM minimum refresh recovery time delay
(tRFC (min.)), MSB
SDRAM minimum internal write to read
command delay (tWTR (min.))
SDRAM minimum internal read to precharge
command delay (tRTP (min.))
27
28
29
30
31
3Ch7.5ns
3Ch7.5ns
Upper nibble for tFAW
00h 30ns
00h 30ns
Minimum four activate window delay time
(tFAW (min.))
F0h 30ns
F0h 30ns
SDRAM optional features
83h DLL-off, RZQ/6, 7
83h DLL-off, RZQ/6, 7
PASR/2X refresh at +85ºC to
+95ºC
PASR/2X refresh at +85ºC to
+95ºC
SDRAM thermal and refresh options
81h
81h
32
33
Module thermal sensor
SDRAM device type
00h Not incorporated
00h Standard
00h Not incorporated
00h Standard
Data Sheet E1795E20 (Ver. 2.0)
5
ELPIDA [ ELPIDA MEMORY ]
