EBE52EC8AAFA
DC Characteristics 1 (TC = 0 to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
Parameter
Symbol Grade
max.
Unit
mA
Test condition
Operating current
(ACT-PRE)
(Another rank is in IDD2P)
-5C
-4A, -4C
1080
927
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD0
Operating current
(ACT-PRE)
(Another rank is in IDD3N)
-5C
-4A, -4C
1575
1395
IDD0
IDD1
mA
mA
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
Operating current
-5C
-4A, -4C
1215
1062
(ACT-READ-PRE)
(Another rank is in IDD2P)
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Operating current
-5C
-4A, -4C
1710
1530
IDD1
mA
mA
(ACT-READ-PRE)
(Another rank is in IDD3N)
all banks idle;
tCK = tCK (IDD);
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
-5C
180
144
450
360
540
450
Precharge power-down
standby current
IDD2P
-4A, -4C
-5C
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet standby
current
IDD2Q
IDD2N
mA
mA
-4A, -4C
-5C
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Idle standby current
-4A, -4C
all banks open;
Fast PDN Exit
tCK = tCK (IDD);
MRS(12) = 0
CKE is L;
-5C
720
630
IDD3P-F
IDD3P-S
mA
mA
-4A, -4C
Active power-down
standby current
Other control and address bus
inputs are STABLE;
-5C
450
360
Slow PDN Exit
MRS(12) = 1
Data bus inputs are FLOATING
-4A, -4C
all banks open;
-5C
1170
1080
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active standby current
IDD3N
mA
-4A, -4C
Operating current
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
-5C
-4A, -4C
1800
1422
IDD4R
IDD4R
IDD4W
mA
mA
mA
(Burst read operating)
(Another rank is in IDD2P)
Operating current
-5C
-4A, -4C
2295
1890
(Burst read operating)
(Another rank is in IDD3N)
Data pattern is same as IDD4W
Operating current
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-5C
-4A, -4C
1800
1422
(Burst write operating)
(Another rank is in IDD2P)
Operating current
-5C
-4A, -4C
2295
1890
IDD4W
IDD5
mA
mA
mA
(Burst write operating)
(Another rank is in IDD3N)
Auto-refresh current
(Another rank is in IDD2P)
-5C
-4A, -4C
2340
2142
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Auto-refresh current
(Another rank is in IDD3N)
-5C
-4A, -4C
2835
2610
IDD5
Preliminary Data Sheet E0468E10 (Ver. 1.0)
11
ELPIDA [ ELPIDA MEMORY ]
