EBE51FD8AHFT, EBE51FD8AHFE, EBE51FD8AHFL
AMB Component Timing
For purposes of IDD testing, the following parameters are to be utilized.
Parameter
Symbol
min.
—
typ.
—
max.
4
Units
clks
Note
tEI
propagate
EI Assertion pass-thru timing
EI deassertion pass-thru timing
EI assertion duration
Resample pass-thru time
Resynch pass-thru Time
Bit lock Interval
tEID
tEI
—
—
bit lock
—
clks
100
—
—
clks
TBD
TBD
—
—
ns
—
—
ns
tBitLock
—
119
154
frames
frames
Frame lock Interval
tFrameLock
—
—
Note: 1. The EI stands for ″Electrical Idle″.
Power Specification Parameter and Test Conditions
-6E
667
-5C
533
Frequency (Mbps)
Parameter
Power
Supply
Symbol
max.
2.60
max.
2.20
Unit
A
Conditions
Note
L0 state, idle (0 BW)
@1.5V
@1.8V
Total
Primary channel enabled,
Secondary channel disabled
Idle Current,
single or last
DIMM
Idd_Idle_0
0.97
5.28
3.40
0.98
6.57
3.90
2.35
9.95
3.70
0.91
4.53
3.00
0.91
5.79
3.40
2.38
9.22
3.20
A
CKE high. Command and address lines stable.
DRAM clock active.
W
A
@1.5V
@1.8V
Total
L0 state, idle (0 BW)
Primary and secondary channels enabled
CKE high. Command and address lines stable.
DRAM clock active.
Idle Current, first
DIMM
Idd_Idle_1
A
W
A
@1.5V
@1.8V
Total
L0 state
50% DRAM BW, 67% read, 33% write.
Primary and secondary channels enabled.
DRAM clock active, CKE high.
Active Power
Idd_Active_1
A
W
A
L0 state
@1.5V
50% DRAM BW to downstream DIMM,
67% read, 33% write.
Active Power,
data pass through
@1.8V
Total
0.97
7.00
0.90
6.09
A
Idd_Active_2
Primary and secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active.
W
Primary and secondary channels enabled.
100% toggle on all channel lanes
DRAMs idle. 0 BW.
@1.5V
@1.8V
Total
4.00
0.94
7.43
3.50
0.89
6.54
A
Idd_Training
(for AMB spec.
Not in SPD)
Training
A
CKE high, Command and address lines stable.
DRAM clock active.
W
Preliminary Data Sheet E1002E30 (Ver. 3.0)
11
ELPIDA [ ELPIDA MEMORY ]
