EBE51FD8AHFT, EBE51FD8AHFE, EBE51FD8AHFL
Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”.
2. Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the
pad will be lower than at the pin.
3. Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as
the Electrical Idle condition. Worst-case margins are determined by comparing EI levels with common
mode levels during normal operation for the case with transmitter using small voltage swing.
4. Multiple lanes need to detect the EI condition before the device can act upon the EI detection.
5. Specified at the package pins into a timing and voltage compliance test setup.
6. Receiver designers may implement either single-ended or differential EI detection. Receivers must meet
the specification that corresponds to the implemented detection circuit.
7. This specification, considered with VTX-IDLE-SE-DC, implies a maximum 15mV single-ended DC offset
between TX and RX pins during the electrical idle condition. This in turn allows a ground offset between
adjacent FB-DIMM agents of 26mV when worst case termination resistance matching is considered.
8. The single-pulse mask provides sufficient symbol energy for reliable RX reception. Each symbol must
comply with both the single-pulse mask and the cumulative eye mask.
9. The relative amplitude ratio limit between adjacent symbols prevents excessive inter-symbol interference
in the Rx. Each symbol must comply with the peak amplitude ratio with regard to both the preceding and
subsequent symbols.
10. This number does not include the effects of SSC or reference clock jitter.
11. This number includes setup and hold of the RX sampling flop.
12. Defined as the dual-dirac deterministic timing error.
13. Allows for 15mV DC offset between transmit and receive devices.
14. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peak-to-
peak common mode specification. For example, if VRX-DIFFp-p is 200mV, the maximum AC peak-to-
peak common mode is the lesser of (200mV × 0.45 = 90mV) and VRX-CM-ACp-p.
15. One of the components that contribute to the deterioration of the return loss is the ESD structure which
needs to be carefully designed.
16. The termination small signal resistance; tolerance across voltages from 100mV to 400mV shall not
exceed ± 5Ω. with regard to the average of the values measured at 100mV and at 400mV for that pin.
17. This number represents the lane-to-lane skew between TX and RX pins and does not include the
transmitter output skew from the component driving the signal to the receiver. This is one component of
the end-to-end channel skew in the AMB specification.
18. Measured from the reference clock edge to the center of the input eye. This specification must be met
across specified voltage and temperature ranges for a single component. Drift rate of change is
significantly below the tracking capability of the receiver.
19. This bandwidth number assumes the specified minimum data transition density. Maximum jitter at 0.2MHz
is 0.05UI.
20. The specified time includes the time required to forward the EI entry condition.
21. BER per differential lane.
Preliminary Data Sheet E1002E30 (Ver. 3.0)
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ELPIDA [ ELPIDA MEMORY ]
