EBE41RE4AAHA
Byte No. Function described
Minimum active to precharge time
(tRAS)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
45ns
30
0
0
1
0
1
1
0
1
2DH
-5C
-4A
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
28H
02H
40ns
2GB
31
32
Module rank density
Address and command setup time
before clock (tIS)
-5C
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
25H
35H
38H
48H
10H
0.25ns*1
0.35ns*1
0.38ns*1
0.48ns*1
0.10ns*1
-4A
Address and command hold time after
clock (tIH)
33
-5C
-4A
Data input setup time before clock
(tDS)
-5C
34
35
-4A
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
1
15H
23H
0.15ns*1
0.23ns*1
Data input hold time after clock (tDH)
-5C
-4A
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
28H
3CH
0.28ns*1
15ns*1
36
37
Write recovery time (tWR)
Internal write to read command delay
(tWTR)
-5C
0
0
0
1
1
1
1
0
1EH
7.5ns*1
-4A
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H
1EH
10ns*1
7.5ns*1
TBD
Internal read to precharge command
delay (tRTP)
38
39
40
Memory analysis probe characteristics 0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
00H
06H
Extension of Byte 41 and 42
0
0
0
0
1
0
0
0
Active command period (tRC)
-5C
41
0
0
1
0
0
0
0
1
1
1
0
0
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
0
3CH
37H
7FH
80H
1EH
23H
28H
60ns*1
-4A
55ns*1
Auto refresh to active/
Auto refresh command cycle (tRFC)
42
43
44
127.5ns*1
8ns*1
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-5C
0.30ns*1
0.35ns*1
0.40ns*1
-4A
Data hold skew (tQHS)
-5C
45
-4A
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
2DH
0FH
00H
10H
0.45ns*1
46
PLL relock time
15µs
47 to 61
62
SPD Revision
Rev. 1.0
Checksum for bytes 0 to 62
-5C
63
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
0
1
7EH
F8H
7FH
-4A
Continuation
code
64 to 65
Manufacturer’s JEDEC ID code
66
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
FEH
00H
Elpida Memory
67 to 71
Data Sheet E0629E20 (Ver. 2.0)
6
ELPIDA [ ELPIDA MEMORY ]
