EBE21UE8AESA
AC Input Test Conditions (DDR2 SDRAM Component Specification)
Parameter
Symbol
Value
0.5 × VDDQ
1.0
Unit
V
Notes
1
Input reference voltage
VREF
Input signal maximum peak to peak swing
Input signal minimum slew rate
VSWING (max.)
SLEW
V
1
1.0
V/ns
2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL (AC) level applied to
the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH (AC) (min.) for
rising edges and the range from VREF to VIL (AC) (max.) for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL (AC) to VIH (AC) on the positive
transitions and VIH (AC) to VIL (AC) on the negative transitions.
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VSWING(max.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
∆TF
VREF
∆TR
−
VIL (AC)(max.)
VIH (AC) min.
−
VREF
Falling slew =
Rising slew =
∆TF
∆TR
AC Input Test Signal Wave forms
Measurement point
DQ
VTT
RT =25 Ω
Output Load
Data Sheet E1298E40 (Ver. 4.0)
22
ELPIDA [ ELPIDA MEMORY ]
