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EBE21UE8AESA 参数 Datasheet PDF下载

EBE21UE8AESA图片预览
型号: EBE21UE8AESA
PDF下载: 下载PDF文件 查看货源
内容描述: 2GB DDR2 SDRAM SO- DIMM [2GB DDR2 SDRAM SO-DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 29 页 / 254 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE21UE8AESA  
CKE (input pin)  
CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the  
CKE is driven low and exited when it resumes to high.  
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge  
and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold  
time tIH.  
DQ (input and output pins)  
Data are input to and output from these pins.  
DQS and /DQS (input and output pin)  
DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input).  
DM (input pins)  
DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and /DQS.  
VDD (power supply pins)  
1.8V is applied. (VDD is for the internal circuit.)  
VDDSPD (power supply pin)  
1.8V is applied (For serial EEPROM).  
VSS (power supply pin)  
Ground is connected.  
Detailed Operation Part and Timing Waveforms  
Refer to the EDE1108AESE, EDE1116AESE datasheet (E1290E).  
Data Sheet E1298E40 (Ver. 4.0)  
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