DATA SHEET
2GB DDR2 SDRAM SO-DIMM
EBE21UE8ACUA(256M words × 64 bits, 2 Ranks)
Specifications
Features
• Density: 2GB
• Double-data-rate architecture; two data transfers per
clock cycle
• Organization
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
256M words × 64 bits, 2 ranks
• Mounting 16 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• Package: 200-pin socket type small outline dual in
line memory module (SO-DIMM)
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
PCB height: 30.0mm
Lead pitch: 0.6mm
• Differential clock inputs (CK and /CK)
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Eight internal banks for concurrent operation
(components)
• Data mask (DM) for write data
• Interface: SSTL_18
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5, 6
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• Precharge: auto precharge option for each burst
• /DQS can be disabled for single-ended Data Strobe
access
operation
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Document No. E1217E10 (Ver. 1.0)
Date Published November 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007
ELPIDA [ ELPIDA MEMORY ]
