EBE21FD4AGFD, EBE21FD4AGFN
Parameter
Symbol
RTX
min.
41
max.
55
Unit
Comments
16
Transmitter termination
resistance
Ω
RTX-Match-DC =
2×|RTX-D+ − RTX-D-| / (RTX-D+
+ RTX-D-)
D+/D- TX resistance
difference
RTX-Match-DC
4
%
Bounds are applied separately to high
and low output voltage states
Lane-to-lane skew at TX
Lane-to-lane skew at TX
LTX-SKEW 1
LTX-SKEW 2
100 + 3UI ps
100 + 2UI ps
17, 19
18, 19
Maximum TX Drift
(resync mode)
TTX-DRIFT-RESYNC
240
ps
ps
20
Maximum TX Drift
(resample mode only)
TTX-DRIFT-
RESAMPLE
120
20
21
Bit Error Ratio
BER
10-12
Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”.
2. Specified at the package pins into a timing and voltage compliance test load. Common-mode
measurements to be performed using a 101010 pattern.
3. The transmitter designer should not artificially elevate the common mode in order to meet this
specification.
4. This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by
the VTX-DIFFp-p of the first bit after a transition.
5. De-emphasis shall be disabled in the calibration state.
6. Includes all sources of AC common mode noise.
7. Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as
the Electrical Idle condition.
8. Specified at the package pins into a voltage compliance test load. Transmitters must meet both single-
ended and differential output EI specifications.
9. This specification, considered with VRX-IDLE-SE-DC, implies a maximum 15mV single-ended DC offset
between TX and RX pins during the electrical idle condition. This in turn allows a ground offset between
adjacent FB-DIMM agents of 26mV when worst case termination resistance matching is considered.
10. The maximum value is specified to be at least (VTX-DIFFp-p L / 4) + VTX-CM L + (VTX-CM-ACp-p / 2)
11. This number does not include the effects of SSC or reference clock jitter.
12. These timing specifications apply to resync mode only.
13. Defined as the dual-dirac deterministic jitter.
14. Pulse width measured at 0 V differential.
15. One of the components that contribute to the deterioration of the return loss is the ESD structure which
needs to be carefully designed.
16. The termination small signal resistance; tolerance across voltages from 100mV to 400mV shall not
exceed ± 5Ω. with regard to the average of the values measured at 100mV and at 400mV for that pin.
17. Lane to Lane skew at the Transmitter pins for an end component.
18. Lane to Lane skew at the Transmitter pins for an intermediate component (assuming zero Lane to Lane
skew at the Receiver pins of the incoming PORT).
19. This is a static skew. An FB-DIMM component is not allowed to change its lane to lane phase relationship
after initialization.
20. Measured from the reference clock edge to the center of the output eye. This specification must be met
across specified voltage and temperature ranges for a single component. Drift rate of change is
significantly below the tracking capability of the receiver.
21. BER per differential lane.
Preliminary Data Sheet E0868E30 (Ver. 3.0)
15
ELPIDA [ ELPIDA MEMORY ]
