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EBE21EE8ACWA-8E-E 参数 Datasheet PDF下载

EBE21EE8ACWA-8E-E图片预览
型号: EBE21EE8ACWA-8E-E
PDF下载: 下载PDF文件 查看货源
内容描述: 2GB无缓冲DDR2 SDRAM DIMM [2GB Unbuffered DDR2 SDRAM DIMM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 30 页 / 242 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE21EE8ACWA  
Parameter  
Symbol Grade  
max.  
Unit  
mA  
Test condition  
Auto-refresh current  
(Another rank is in IDD2P)  
-8E, -8G  
2700  
2610  
IDD5  
IDD5  
IDD6  
-6E  
tCK = tCK (IDD);  
Refresh command at every tRFC (IDD) interval;  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Auto-refresh current  
(Another rank is in IDD3N)  
-8E, -8G  
-6E  
3420  
3240  
mA  
mA  
Self Refresh Mode;  
CK and /CK at 0V;  
CKE 0.2V;  
Self-refresh current  
180  
Other control and address bus inputs are FLOATING;  
Data bus inputs are FLOATING  
all bank interleaving reads, IOUT = 0mA;  
Operating current  
-8E, -8G  
-6E  
2700  
2565  
BL = 4, CL = CL(IDD), AL = tRCD (IDD) 1 × tCK (IDD);  
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),  
tFAW = tFAW (IDD), tRCD = 1 × tCK (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are STABLE during DESELECTs;  
Data pattern is same as IDD4W;  
IDD7  
IDD7  
mA  
mA  
(Bank interleaving)  
(Another rank is in IDD2P)  
Operating current  
-8E, -8G  
-6E  
3420  
3195  
(Bank interleaving)  
(Another rank is in IDD3N)  
Notes: 1. IDD specifications are tested after the device is properly initialized.  
2. Input slew rate is specified by AC Input Test Condition.  
3. IDD parameters are specified with ODT disabled.  
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all  
combinations of EMRS bits 10 and 11.  
5. Definitions for IDD  
L is defined as VIN VIL (AC) (max.)  
H is defined as VIN VIH (AC) (min.)  
STABLE is defined as inputs stable at an H or L level  
FLOATING is defined as inputs at VREF = VDDQ/2  
SWITCHING is defined as:  
inputs changing between H and L every other clock cycle (once per two clocks) for address and control  
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals  
not including masks or strobes.  
6. Refer to AC Timing for IDD Test Conditions.  
Data Sheet E1215E10 (Ver. 1.0)  
13  
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