EBE20AE4ACWA
ODT DC Electrical Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol
Rtt1(eff)
Rtt2(eff)
Rtt3(eff)
∆VM
min.
60
typ.
75
max.
90
Unit
Ω
Note
Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Ω
Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Ω
Rtt effective impedance value for EMRS (A6, A2) = 1, 1; 50 Ω
Deviation of VM with respect to VDDQ/2
1
1
1
1
120
40
150
50
180
60
Ω
Ω
−6
+6
%
Note: 1. Test condition for Rtt measurements.
Measurement Definition for Rtt (eff)
Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively.
VIH(AC), and VDDQ values defined in SSTL_18.
VIH(AC) −VIL(AC)
Rtt(eff ) =
I(VIH(AC))− I(VIL(AC))
Measurement Definition for ∆VM
Measure voltage (VM) at test pin (midpoint) with no load.
2×VM
∆VM =
-1 ×100
VDDQ
OCD Default Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
min.
12.6
0
typ.
18
max.
23.4
4
Unit
Ω
Notes
1, 5
Output impedance
Pull-up and pull-down mismatch
Output slew rate
Ω
1, 2
1.5
5
V/ns
3, 4
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV;
(VOUT−VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and VDDQ−280mV.
Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV;
VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and 280mV.
2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and
voltage.
3. Slew rate measured from VIL(AC) to VIH(AC).
4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate
as measured from AC to AC. This is guaranteed by design and characterization.
5. DRAM I/O specifications for timing, voltage, and slew rate are no longer applicable if OCD is changed
from default settings.
Pin Capacitance (TA = 25°C, VDD = 1.8V ± 0.1V)
Parameter
Symbol
CI1
Pins
min.
2.0
max.
3.5
Unit
pF
Notes
Address, /RAS, /CAS, /WE,
/CS, CKE, ODT
Input capacitance
Input capacitance
1
2
CI2
CK, /CK
2.0
3.0
pF
DQ, DQS, /DQS, UDQS,
/UDQS, LDQS, /LDQS,
RDQS, /RDQS, DM,
UDM, LDM, CB
Input/output pin capacitance CI/O
2.5
3.5
pF
3
Notes: 1. Register component specification.
2. PLL component specification.
3. DDR2 SDRAM component specification.
Data Sheet E1395E10 (Ver. 1.0)
15
ELPIDA [ ELPIDA MEMORY ]
