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EBE11UE6ACUA-6E-E 参数 Datasheet PDF下载

EBE11UE6ACUA-6E-E图片预览
型号: EBE11UE6ACUA-6E-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB DDR2 SDRAM SO- DIMM [1GB DDR2 SDRAM SO-DIMM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 27 页 / 287 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE11UE6ACUA  
Parameter  
Symbol  
IDD5  
Grade  
max.  
Unit  
mA  
Test condition  
Auto-refresh current  
(Another rank is in IDD2P)  
-8E, -8G 1200  
-6E 1160  
tCK = tCK (IDD);  
Refresh command at every tRFC (IDD) interval;  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Auto-refresh current  
(Another rank is in IDD3N)  
-8E, -8G 1520  
-6E  
IDD5  
IDD6  
mA  
mA  
1440  
Self Refresh Mode;  
CK and /CK at 0V;  
Self-refresh current  
80  
CKE 0.2V;  
Other control and address bus inputs are FLOATING;  
Data bus inputs are FLOATING  
all bank interleaving reads, IOUT = 0mA;  
Operating current  
-8E, -8G 1440  
-6E 1280  
BL = 4, CL = CL(IDD), AL = tRCD (IDD) 1 × tCK (IDD);  
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),  
tFAW = tFAW (IDD), tRCD = 1 × tCK (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are STABLE during DESELECTs;  
Data pattern is same as IDD4W;  
IDD7  
IDD7  
mA  
mA  
(Bank interleaving)  
(Another rank is in IDD2P)  
Operating current  
-8E, -8G 1760  
-6E 1560  
(Bank interleaving)  
(Another rank is in IDD3N)  
Notes: 1. IDD specifications are tested after the device is properly initialized.  
2. Input slew rate is specified by AC Input Test Condition.  
3. IDD parameters are specified with ODT disabled.  
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all  
combinations of EMRS bits 10 and 11.  
5. Definitions for IDD  
L is defined as VIN VIL (AC) (max.)  
H is defined as VIN VIH (AC) (min.)  
STABLE is defined as inputs stable at an H or L level  
FLOATING is defined as inputs at VREF = VDDQ/2  
SWITCHING is defined as:  
inputs changing between H and L every other clock cycle (once per two clocks) for address and control  
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals  
not including masks or strobes.  
6. Refer to AC Timing for IDD Test Conditions.  
AC Timing for IDD Test Conditions  
For purposes of IDD testing, the following parameters are to be utilized.  
DDR2-800  
DDR2-800  
DDR2-667  
Parameter  
5-5-5  
5
6-6-6  
6
5-5-5  
5
Unit  
tCK  
ns  
CL (IDD)  
tRCD (IDD)  
tRC (IDD)  
12.5  
57.5  
10  
15  
15  
60  
60  
ns  
tRRD (IDD)  
tFAW (IDD)  
tCK (IDD)  
10  
10  
ns  
45  
45  
50  
ns  
2.5  
2.5  
45  
3
ns  
tRAS (min.)(IDD)  
tRAS (max.)(IDD)  
tRP (IDD)  
45  
45  
ns  
70000  
12.5  
127.5  
70000  
15  
70000  
15  
ns  
ns  
tRFC (IDD)  
127.5  
127.5  
ns  
Data Sheet E1216E10 (Ver. 1.0)  
12  
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