EBE11ED8AJWA
-8E
-8G
-6E
DDR2-667 (5-5-5)
Speed bin
Parameter
DDR2-800 (5-5-5)
DDR2-800 (6-6-6)
Symbol min.
max.
min.
0.2
max.
min.
0.2
max.
Unit Notes
DQS falling edge hold time from
CK
tCK
(avg)
tDSH
tMRD
0.2
2
Mode register set command
cycle time
2
2
nCK
tCK
(avg)
Write postamble
Write preamble
tWPST 0.4
tWPRE 0.35
0.6
0.4
0.35
250
175
0.9
0.4
0.6
0.4
0.35
275
200
0.9
0.4
0.6
tCK
(avg)
Address and control input hold
time
tIH
(base)
250
ps
ps
5
Address and control input setup tIS
time
175
0.9
0.4
4
(base)
tCK
(avg)
Read preamble
tRPRE
tRPST
1.1
1.1
1.1
11
12
tCK
(avg)
Read postamble
0.6
0.6
0.6
Active to precharge command
Active to auto-precharge delay
tRAS
tRAP
45
70000
45
70000
45
70000
ns
ns
tRCD min.
tRCD min.
tRCD min.
Active bank A to active bank B
command period
tRRD
7.5
7.5
7.5
ns
/CAS to /CAS command delay
Write recovery time
tCCD
tWR
2
2
2
nCK
ns
15
15
15
WR +
RU (tRP/
tCK (avg))
WR +
RU (tRP/
tCK (avg))
WR +
RU (tRP/
tCK (avg))
Auto precharge write recovery +
precharge time
tDAL
nCK 1, 9
Internal write to read command
delay
tWTR
tRTP
7.5
7.5
7.5
ns
14
Internal read to precharge
command delay
7.5
7.5
7.5
ns
Exit self-refresh to a non-read
command
tXSNR
tXSRD
tXP
tRFC + 10
tRFC + 10
tRFC + 10
ns
Exit self-refresh to a read
command
200
2
200
2
200
2
nCK
nCK
nCK
Exit precharge power down to
any non-read command
Exit active power down to read
command
tXARD
2
2
2
3
Exit active power down to read
command
tXARDS 8 − AL
8 − AL
7 − AL
nCK 2, 3
(slow exit/low power mode)
CKE minimum pulse width
(high and low pulse width)
tCKE
tOIT
3
3
3
nCK
ns
Output impedance test driver
delay
0
12
12
0
12
12
0
12
12
MRS command to ODT update
delay
tMOD
tRFC
0
0
0
ns
Auto-refresh to active/auto-
refresh command time
105
105
105
ns
Average periodic refresh interval
(0°C ≤ TC ≤ +85°C)
tREFI
tREFI
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
(+85°C < TC ≤ +95°C)
Minimum time clocks remains
ON after CKE asynchronously
drops low
tIS +
tIS +
tCK(avg) +
tIH
tIS +
tCK(avg) +
tIH
tDELAY tCK(avg) +
ns
tIH
Data Sheet E1054E30 (Ver. 3.0)
18