EBE10UE8AEFA
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
(DDR2 SDRAM Component Specification)
• New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
-8G
-6E
DDR2-667 (5-5-5)
Speed bin
DDR2-800 (6-6-6)
Parameter
Symbol
tRCD
tRP
min.
15
max.
min.
15
max.
Unit
ns
Notes
Active to read or write command delay
Precharge command period
15
15
ns
Active to active/auto-refresh command time tRC
60
60
ns
DQ output access time from CK, /CK
DQS output access time from CK, /CK
CK high-level width
tAC
−400
−350
+400
+350
0.52
0.52
−450
−400
0.48
0.48
+450
+400
0.52
0.52
ps
10
10
tDQSCK
ps
tCH (avg) 0.48
tCK (avg) 13
tCK (avg) 13
CK low-level width
tCL(avg)
0.48
Min.
Min.
CK half period
tHP
(tCL(abs),
tCH(abs))
(tCL(abs),
tCH(abs))
ps
ps
6, 13
Clock cycle time
(CL = 6)
tCK (avg) 2500
8000
3000
8000
13
(CL = 5)
tCK (avg) 3000
tCK (avg) 3750
tCK (avg) 5000
tDH (base) 125
tDS (base) 50
8000
8000
8000
3000
3750
5000
175
8000
8000
8000
ps
ps
ps
ps
ps
13
13
13
5
(CL = 4)
(CL = 3)
DQ and DM input hold time
DQ and DM input setup time
100
4
Control and Address input pulse width for
each input
tIPW
0.6
0.6
tCK (avg)
DQ and DM input pulse width for each input tDIPW
0.35
0.35
tCK (avg)
ps
Data-out high-impedance time from CK,/CK tHZ
DQS, /DQS low-impedance time from
tAC max.
tAC max.
tAC max.
tAC max.
10
10
tLZ (DQS) tAC min.
tAC min.
ps
ps
ps
CK,/CK
2
tLZ (DQ)
2
DQ low-impedance time from CK,/CK
tAC max.
tAC max.
10
× tAC min
× tAC min
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
tQHS
200
300
240
340
DQ hold skew factor
ps
ps
7
8
DQ/DQS output hold time from DQS
tQH
tHP – tQHS
tHP – tQHS
DQS latching rising transitions to associated
clock edges
tDQSS
−0.25
+0.25
−0.25
+0.25
tCK (avg)
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
0.35
0.35
0.2
tCK (avg)
tCK (avg)
tCK (avg)
tCK (avg)
nCK
tDSH
0.2
tMRD
2
tWPST
tWPRE
0.4
0.35
0.6
1.1
0.4
0.35
275
200
0.9
0.6
1.1
tCK (avg)
tCK (avg)
ps
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
tIH (base) 250
tIS (base) 175
5
4
ps
tRPRE
0.9
tCK (avg) 11
Data Sheet E1295E40 (Ver. 4.0)
18