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EBE10RD4ABFA 参数 Datasheet PDF下载

EBE10RD4ABFA图片预览
型号: EBE10RD4ABFA
PDF下载: 下载PDF文件 查看货源
内容描述: 注册1GB DDR2 SDRAM DIMM ( 128M字× 72位,1个等级) [1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 22 页 / 171 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE10RD4ABFA的Datasheet PDF文件第2页浏览型号EBE10RD4ABFA的Datasheet PDF文件第3页浏览型号EBE10RD4ABFA的Datasheet PDF文件第4页浏览型号EBE10RD4ABFA的Datasheet PDF文件第5页浏览型号EBE10RD4ABFA的Datasheet PDF文件第7页浏览型号EBE10RD4ABFA的Datasheet PDF文件第8页浏览型号EBE10RD4ABFA的Datasheet PDF文件第9页浏览型号EBE10RD4ABFA的Datasheet PDF文件第10页  
EBE10RD4ABFA  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value  
Comments  
15ns  
Minimum row precharge time (tRP)  
27  
28  
29  
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
3CH  
1EH  
3CH  
-5C, -4A  
Minimum row active to row active delay  
(tRRD)  
7.5ns  
15ns  
Minimum /RAS to /CAS delay (tRCD)  
-5C, -4A  
Minimum active to precharge time  
(tRAS)  
30  
31  
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
1
2DH  
01H  
45ns  
1GB  
Module rank density  
Address and command setup time  
before clock (tIS)  
-5C  
32  
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
25H  
35H  
38H  
48H  
10H  
0.25ns*1  
0.35ns*1  
0.38ns*1  
0.48ns*1  
0.10ns*1  
-4A  
Address and command hold time after  
clock (tIH)  
33  
-5C  
-4A  
Data input setup time before clock  
(tDS)  
-5C  
34  
35  
-4A  
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
1
15H  
23H  
0.15ns*1  
0.23ns*1  
Data input hold time after clock (tDH)  
-5C  
-4A  
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
28H  
3CH  
0.28ns*1  
15ns*1  
36  
37  
Write recovery time (tWR)  
Internal write to read command delay  
(tWTR)  
-5C  
0
0
0
1
1
1
1
0
1EH  
7.5ns*1  
-4A  
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H  
1EH  
10ns*1  
7.5ns*1  
Internal read to precharge command  
delay (tRTP)  
38  
39  
40  
Memory analysis probe characteristics 0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00H  
00H  
TBD  
Extension of Byte 41 and 42  
0
0
Undefined  
Active command period (tRC)  
-5C, -4A  
41  
0
1
1
1
1
0
0
3CH  
60ns*1  
Auto refresh to active/  
Auto refresh command cycle (tRFC)  
42  
43  
44  
0
1
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
0
0
0
0
1
1
0
1
0
0
1
0
69H  
80H  
1EH  
23H  
28H  
105ns*1  
8ns*1  
SDRAM tCK cycle max. (tCK max.)  
Dout to DQS skew  
-5C  
0.30ns*1  
0.35ns*1  
0.40ns*1  
-4A  
Data hold skew (tQHS)  
-5C  
45  
-4A  
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
1
0
2DH  
0FH  
00H  
0.45ns*1  
46  
PLL relock time  
15µs  
47 to 61  
Data Sheet E0366E70 (Ver. 7.0)  
6