EBD52UC8AKFA-5-E
-5B
-5C
Parameter
Symbol
tRFC
min.
max.
—
min.
max.
—
Unit
ns
Notes
Auto refresh to Active/Auto refresh
command period
70
70
Active to Read/Write delay
Precharge to active command period
Active to Autoprecharge delay
Active to active command period
Write recovery time
tRCD
tRP
15
—
—
—
—
—
18
—
—
—
—
—
ns
ns
ns
ns
ns
15
18
tRAP
tRRD
tWR
tRCD min.
tRCD min.
10
15
10
15
Auto precharge write recovery and
precharge time
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tDAL
—
—
tCK
13
Internal write to Read command delay
tWTR
tREF
2
—
2
—
tCK
µs
Average periodic refresh interval
—
7.8
—
7.8
Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions,
refer to the corresponding component data sheet.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.6V ± 0.1V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –5C Speed at CL = 3, tCK = 5ns, tWR = 15ns and tRP= 18ns,
tDAL = (15ns/5ns) + (18ns/5ns) = (3) + (4)
tDAL = 7 clocks
Preliminary Data Sheet E0601E10 (Ver. 1.0)
13
ELPIDA [ ELPIDA MEMORY ]
