欢迎访问ic37.com |
会员登录 免费注册
发布采购

EBD25UC8AJFA-6B 参数 Datasheet PDF下载

EBD25UC8AJFA-6B图片预览
型号: EBD25UC8AJFA-6B
PDF下载: 下载PDF文件 查看货源
内容描述: 256MB无缓冲DDR SDRAM DIMM [256MB Unbuffered DDR SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 19 页 / 192 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBD25UC8AJFA-6B的Datasheet PDF文件第2页浏览型号EBD25UC8AJFA-6B的Datasheet PDF文件第3页浏览型号EBD25UC8AJFA-6B的Datasheet PDF文件第4页浏览型号EBD25UC8AJFA-6B的Datasheet PDF文件第5页浏览型号EBD25UC8AJFA-6B的Datasheet PDF文件第6页浏览型号EBD25UC8AJFA-6B的Datasheet PDF文件第7页浏览型号EBD25UC8AJFA-6B的Datasheet PDF文件第8页浏览型号EBD25UC8AJFA-6B的Datasheet PDF文件第9页  
PRELIMINARY DATA SHEET  
1GB Registered DDR SDRAM DIMM  
EBD10RD4ABFA (128M words × 72 bits, 1 Rank)  
Description  
Features  
The EBD10RD4ABFA is 128M words × 72 bits, 1 rank  
Double Data Rate (DDR) SDRAM registered module,  
mounting 18 pieces of 512M bits DDR SDRAM sealed  
in TSOP package. Read and write operations are  
performed at the cross points of the CK and the /CK.  
This high-speed data transfer is realized by the 2-bit  
prefetch-pipelined architecture. Data strobe (DQS)  
both for read and write are available for high speed and  
reliable data bus design. By setting extended mode  
register, the on-chip Delay Locked Loop (DLL) can be  
set enable or disable. This module provides high  
density mounting without utilizing surface mount  
184-pin socket type dual in line memory module  
(DIMM)  
PCB height: 30.48mm  
Lead pitch: 1.27mm  
2.5V power supply  
Data rate: 333Mbps/266Mbps (max.)  
2.5 V (SSTL_2 compatible) I/O  
Double Data Rate architecture; two data transfers per  
clock cycle  
Bi-directional, data strobe (DQS) is transmitted  
/received with data, to be used in capturing data at  
the receiver  
technology.  
Decoupling capacitors are mounted  
beside each TSOP on the module board.  
Data inputs and outputs are synchronized with DQS  
4 internal banks for concurrent operation  
(Component)  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Auto precharge option for each burst access  
Programmable burst length: 2, 4, 8  
Programmable /CAS latency (CL): 2, 2.5  
Refresh cycles: (8192 refresh cycles /64ms)  
7.8µs maximum average periodic refresh interval  
2 variations of refresh  
Auto refresh  
Self refresh  
1 piece of PLL clock driver, 2 pieces of register driver  
and 1 piece of serial EEPROM (2k bits) for Presence  
Detect (SPD) on PCB.  
Document No. E0274E40 (Ver. 4.0)  
Date Published April 2003 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory,Inc. 2002-2003