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EBD25RB4ALFA 参数 Datasheet PDF下载

EBD25RB4ALFA图片预览
型号: EBD25RB4ALFA
PDF下载: 下载PDF文件 查看货源
内容描述: 注册256MB DDR SDRAM DIMM [256MB Registered DDR SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 17 页 / 130 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBD25RB4ALFA的Datasheet PDF文件第1页浏览型号EBD25RB4ALFA的Datasheet PDF文件第2页浏览型号EBD25RB4ALFA的Datasheet PDF文件第3页浏览型号EBD25RB4ALFA的Datasheet PDF文件第4页浏览型号EBD25RB4ALFA的Datasheet PDF文件第6页浏览型号EBD25RB4ALFA的Datasheet PDF文件第7页浏览型号EBD25RB4ALFA的Datasheet PDF文件第8页浏览型号EBD25RB4ALFA的Datasheet PDF文件第9页  
EBD25RB4ALFA  
Serial PD Matrix  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value  
Comments  
128 bytes  
Number of bytes utilized by module  
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H  
08H  
manufacturer  
Total number of bytes in serial PD  
device  
256 bytes  
2
3
4
5
6
7
8
Memory type  
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
0
0
1
0
1
1
0
0
0
07H  
0CH  
0BH  
01H  
48H  
00H  
04H  
DDR SDRAM  
Number of row address  
Number of column address  
Number of DIMM banks  
Module data width  
12  
11  
1
72 bits  
0
Module data width continuation  
Voltage interface level of this assembly 0  
SSTL 2  
DDR SDRAM cycle time, CL = 2.5  
(-7A)  
9
0
1
1
1
0
1
0
1
75H  
7.5ns  
(-75)  
(-1A)  
0
1
1
0
1
1
1
0
0
0
1
0
0
0
1
0
75H  
A0H  
7.5ns  
10ns  
SDRAM access from clock (tAC)  
(-7A)  
10  
0
1
1
1
0
1
0
1
75H  
0.75ns  
(-75)  
0
1
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
1
0
0
0
0
0
75H  
80H  
02H  
80H  
04H  
04H  
0.75ns  
0.8ns  
ECC  
Norm  
× 4  
(-1A)  
11  
12  
13  
14  
DIMM configuration type  
Refresh rate/type  
Primary SDRAM width  
Error checking SDRAM width  
× 4  
SDRAM device attributes:  
Minimum clock delay back-to-back  
column access  
15  
0
0
0
0
0
0
0
1
01H  
1 CLK  
SDRAM device attributes:  
Burst length supported  
16  
17  
18  
19  
20  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0EH  
04H  
0CH  
01H  
02H  
2, 4, 8  
SDRAM device attributes: Number of  
banks on SDRAM device  
4
SDRAM device attributes:  
/CAS latency  
2, 2.5  
SDRAM device attributes:  
/CS latency  
SDRAM device attributes:  
/WE latency  
0
1
21  
22  
SDRAM module attributes  
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
26H  
00H  
Reg+PLLdifclk  
VDD 0.2V  
SDRAM device attributes: General  
Minimum clock cycle time at CL = 2  
(-7A)  
23  
0
1
1
1
0
1
0
1
75H  
7.5ns  
(-75)  
(-1A)  
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
A0H  
A0H  
10ns  
10ns  
Maximum data access time (tAC) from  
24  
clock at CL = 2  
(-7A)  
0
1
1
1
0
1
0
1
75H  
0.75ns  
(-75)  
(-1A)  
0
1
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
75H  
80H  
00H  
0.75ns  
0.8ns  
25 to 26  
Preliminary Data Sheet E0211E11 (Ver. 1.1)  
5