EBD13UB6ALS
Pin Capacitance (TA = 25°C, VDD = 2.5V 0.2V)
Parameter
Symbol
CI1
Pins
max.
TBD
TBD
TBD
Unit
pF
Notes
Address, /RAS, /CAS, /WE,
/CS, CKE
Input capacitance
Input capacitance
CI2
CLK, /CLK
pF
Data and DQS input/output
capacitance
CO
DQ, DQS
pF
AC Characteristics (TA = 0 to +70°C, VDD = 2.5V 0.2V, VSS = 0V)
Synchronous Characteristics
-7A
-75
-1A
Parameter
Symbol min.
max. min.
max. min.
max.
12
Unit
Note
Clock cycle time
CL = 2.5
tCK
7.5
12
7.5
12
12
10
10
ns
CL = 2
7.5
12
10
12
ns
tCK
tCK
ns
CLK high-level width
tCH
tCL
tAC
0.45
0.45
–0.75
0.55
0.55
0.75
0.75
0.45
0.45
–0.75
–0.75
0.55 0.45
0.55 0.45
0.75 –0.8
0.75 –0.8
0.55
0.55
0.8
CLK low-level width
DQ output access time from CLK, /CLK
DQS output access time from CLK, /CLK
tDQSCK –0.75
0.8
ns
DQS-DQ skew (for DQS and associated DQ
signals)
tDQSQ
—
0.5
—
0.5
0.5
—
—
0.6
ns
DQS-DQ skew (for DQS and all DQ signals) tDQSQA —
0.5
—
0.6
0.8
ns
ns
Data out low-impedance time from CLK, /CLKtLZ
–0.75
0.75
–0.75
0.75 –0.8
0.75 –0.8
Data out high-impedance time from CLK,
/CLK
tHZ
–0.75
0.75
–0.75
0.8
ns
Half clock period
tHP
tCH, tCL
—
tCH, tCL
0.9
—
tCH, tCL —
ns
tCK
tCK
ns
Read preamble
tRPRE 0.9
1.1
0.6
1.1
0.6
0.9
0.4
tHP – 1
0.6
0.6
2
1.1
0.6
—
Read postamble
tRPST
tQH
0.4
0.4
DQ/DQS output hold time from DQS
DQ and DM input setup time
DQ and DM input hold time
tHP – 0.75 —
tHP – 0.75 —
tDS
0.5
—
—
—
—
—
0.6
0.5
0.5
1.75
0
—
—
—
—
—
0.6
—
ns
tDH
0.5
—
ns
DQ and DM input pulse width (for each input) tDIPW
1.75
—
ns
Write preamble setup time
Write preamble
tWPRES 0
0
—
ns
tWPRE 0.25
tWPST 0.4
0.25
0.4
0.25
0.4
—
tCK
tCK
Write postamble
0.6
Write command to first DQS latching
transition
tDQSS 0.75
1.25
0.75
1.25 0.75
1.25
tCK
DQS input high pulse width
tDQSH 0.35
tDQSL 0.35
—
—
—
—
—
—
—
—
0.35
0.35
0.2
0.2
0.9
0.9
2.2
1
—
—
—
—
—
—
—
—
0.35
0.35
0.2
0.2
1.1
1.1
2.5
1
—
—
—
—
—
—
—
—
tCK
tCK
tCK
tCK
ns
DQS input low pulse width
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Internal write to read command delay
tDSS
tDSH
tIS
0.2
0.2
0.9
0.9
2.2
1
tIH
ns
tIPW
tWTR
ns
tCK
Preliminary Data Sheet E0219E10 (Ver. 1.0)
12
ELPIDA [ ELPIDA MEMORY ]
