EBD11UD8ADDA
Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V)
Parameter
Symbol
CI1
Pins
max.
Unit
pF
Notes
1, 3
Input capacitance
Input capacitance
Input capacitance
Address, /RAS, /CAS, /WE 90
CI2
CK, /CK
70
60
pF
1, 3
CI3
CKE, /CS
pF
1, 3
Data and DQS input/output
capacitance
CO
DQ, DQS, DM
30
pF
1, 2, 3
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100%tested.
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
-6B
-7A
-7B
Parameter
Symbol min.
max.
12
min.
max.
12
min.
max.
12
Unit
ns
Notes
10
Clock cycle time
(CL = 2)
tCK
7.5
7.5
10
(CL = 2.5)
tCK
tCH
tCL
6
12
7.5
12
7.5
12
ns
CK high-level width
CK low-level width
0.45
0.55
0.55
0.45
0.55
0.55
0.45
0.55
0.55
tCK
tCK
0.45
0.45
0.45
min
min
min
CK half period
tHP
tAC
—
—
—
tCK
ns
(tCH, tCL)
(tCH, tCL)
(tCH, tCL)
DQ output access time from
CK, /CK
–0.7
0.7
–0.75
0.75
–0.75
0.75
2, 11
DQS output access time from CK,
tDQSCK –0.6
0.6
–0.75
—
0.75
0.5
–0.75
—
0.75
0.5
ns
ns
ns
ns
ns
2, 11
3
/CK
DQS to DQ skew
DQ/DQS output hold time from
DQS
Data hold skew factor
Data-out high-impedance time from
CK, /CK
tDQSQ
tQH
—
0.45
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
tQHS
tHZ
—
0.55
—
0.75
—
0.75
–0.7
0.7
0.7
–0.75
0.75
0.75
–0.75
0.75
0.75
5, 11
6, 11
Data-out low-impedance time from
CK, /CK
tLZ
–0.7
–0.75
–0.75
ns
Read preamble
tRPRE 0.9
tRPST 0.4
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
tCK
tCK
ns
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
tDS
tDH
0.45
0.45
8
8
7
—
—
—
ns
tDIPW 1.75
tWPRES 0
—
—
—
ns
—
—
—
ns
tWPRE 0.25
tWPST 0.4
—
0.25
0.4
—
0.25
0.4
—
tCK
tCK
Write postamble
0.6
0.6
0.6
9
Write command to first DQS
latching transition
tDQSS 0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK setup time tDSS
0.2
0.2
—
—
—
—
0.2
—
—
—
—
0.2
—
—
—
—
tCK
tCK
tCK
tCK
DQS falling edge hold time from CK tDSH
0.2
0.2
DQS input high pulse width
DQS input low pulse width
tDQSH 0.35
tDQSL 0.35
0.35
0.35
0.35
0.35
Address and control input setup
time
tIS
0.75
—
0.9
—
0.9
—
ns
8
Data Sheet E0431E20 (Ver. 2.0)
12
ELPIDA [ ELPIDA MEMORY ]
